Commit graph

105005 commits

Author SHA1 Message Date
Alyssa Rosenzweig
7103baf01f panfrost/decode: Drop _replay prefix
We don't even support replay anymore; this is just wasting characters
and adding clutter.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-12 16:23:53 -07:00
Alyssa Rosenzweig
0d5abfdec5 panfrost/decode: Drop _name suffixes
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-12 16:23:53 -07:00
Alyssa Rosenzweig
0c1874adad panfrost/decode: Add MEMORY_PROP_DIR variant
This allows dumping memory properties directly without dereferencing an
address, allowing us to fix more -Waddress-of-packed-member warnings.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-12 16:23:52 -07:00
Alyssa Rosenzweig
9ffe061c5e panfrost/decode: Copy embedded structs before using
Fixes some, but not all, warnings from -Waddress-of-packed-member

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-12 16:23:52 -07:00
Alyssa Rosenzweig
23b230d72f panfrost/decode: Remove pandecode_decode_fbd_type
It is unused.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-12 16:23:52 -07:00
Alyssa Rosenzweig
9eea8423a0 panfrost/midgard: Use generic outmod type
It could be midgard_outmod_float or midgard_outmod_int; don't assume
it's one or the other. Fixes -Wenum-conversion warnings.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-12 16:23:52 -07:00
Alyssa Rosenzweig
e173d6b1b1 panfrost: Precompute scoreboard dependents
Mali job dependency graphs, at least for GLES3.0, have the special
property that a given node will only have at most a single dependent.
This allows us to efficiently precompute the dependent array and
replace an inner loop's O(N) search with an O(1) lookup, bringing the
algorithmic complexity of scoreboarding from O(N^2) to O(N).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-12 16:22:15 -07:00
Alyssa Rosenzweig
b68778e6de panfrost: Remove transient pool abstraction
Now that it has been totally replaced by the borrow mechanism, it is now
unused code.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-12 15:31:48 -07:00
Alyssa Rosenzweig
ee32700f37 panfrost: Subdivide fixed-size transient slabs
The whole purpose of the transient memory model is to make subdivision
stupidly easy, so let's handle that.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-12 15:31:48 -07:00
Alyssa Rosenzweig
37097b2f38 panfrost: Recycle fixed-size transient BOs
The usual case. We use the bitset to mark freedom and seize it.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-12 15:31:48 -07:00
Alyssa Rosenzweig
0f5ad9efcc panfrost: Bookkeep transient indices
The batch now temporarily possesses the transient buffer, so it'll need
to remember that to free it later.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-12 15:31:48 -07:00
Alyssa Rosenzweig
00c9a1cb75 panfrost: Rewrite allocate_transient with new abstraction
We use a fixed size slab if we can, otherwise we create a dedicated
("oversized") BO and add that to the job. In the latter case we'll get
reference counting for free so we can forget about this corner case for
the rest of the series.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-12 15:31:48 -07:00
Alyssa Rosenzweig
ba02cf0e75 panfrost: Add pan_bo_for_screen helper
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-12 15:31:48 -07:00
Alyssa Rosenzweig
330cd057ad panfrost: Add panfrost_transient_bo array
We would like transient allocations to occur on the screen (borrowed by
the batch) rather than on the context. Add fields to track this.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-12 15:31:47 -07:00
Alyssa Rosenzweig
718ebfa225 panfrost: Don't upload vertex/tiler twice
The latter upload is correct, but the former upload is unassociated with
any particular FBO and therefore becomes orphaned. We do have to upload
at draw-time at the latest, if we haven't by then.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-12 15:31:47 -07:00
Alyssa Rosenzweig
085004cc2c panfrost/drm: Check allocation size is positive
Zero-sized allocations will fail with an unhelpful errno from the
kernel; check size explicitly in userspace before it gets that far.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-12 15:31:47 -07:00
Neil Roberts
8419621176 mesa/glspirv: Validate that compute shaders are not linked with other stages
The test is based on link_shaders().

For example, it allows the following test (when run on SPIR-V mode) to
pass:
   spec/arb_compute_shader/linker/mix_compute_and_non_compute.shader_test

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-07-12 23:42:42 +02:00
Neil Roberts
022e9ddd1a mesa/glspirv: Validate that there is a VS when there is a TCS, TES or GS
The shader combination tests are copied from link_shaders().

For example, it allows the following tests (when run on SPIR-V mode) to
pass:
   spec/arb_tessellation_shader/linker/no-vs
   spec/arb_tessellation_shader/linker/tcs-no-vs
   spec/arb_tessellation_shader/linker/tes-no-vs
   spec/glsl-1.50/linker/gs-without-vs

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-07-12 23:42:41 +02:00
Alejandro Piñeiro
e4210b93e4 i965: don't use disk cache with SPIR-V shaders
Right now we don't support disk cache for SPIR-V shaders (from
ARB_gl_spirv), so let's avoid writing the program data to or reading
it from the disk if any in-use shaders use SPIR-V.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-07-12 23:42:41 +02:00
Alejandro Piñeiro
bb3bbdfbbd glsl/shader_cache: handle SPIR-V shaders
Right now we don't have cache support for SPIR-V shaders (from
ARB_gl_spirv). Right now they are properly skipped because they fall
on the ff shader code path (no key, no name), but it would be better
to update current comments, and add some guards.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-07-12 23:42:41 +02:00
Arcady Goldmints-Orlov
637b168470 nir/linker: Initialize UniformDataDefaults when using SPIR-V
Allocate UniformDataDefaults and fill in the data defaults when
linking a SPIR-V program. Among other things, this allows program
serialization to work.

It allows the following piglit test (when run on SPIR-V mode) to pass:
  spec/arb_get_program_binary/execution/uniform-after-restore.shader_test

v2: use memcpy to initialize UniformDataDefaults

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-07-12 23:42:41 +02:00
Arcady Goldmints-Orlov
761b0fe95f glsl/serialize: Update write_program_resource_data() to handle NULL input and output variable names
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-07-12 23:42:41 +02:00
Arcady Goldmints-Orlov
c3122d2431 glsl/serialize: Handle NULL uniform name in write_uniforms()
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-07-12 23:42:41 +02:00
Antia Puentes
0baa553fab mesa/main: Fix UBO/SSBO ACTIVE_VARIABLES query (ARB_gl_spirv)
When querying MAX_NUM_ACTIVE_VARIABLES, NUM_ACTIVE_VARIABLES and
ACTIVE_VARIABLES over SSBO and UBO interfaces, we filter the variables
which are active using the variable's name and looking for it in the
program resource list. If it is in the program resource list, the
variable will be considered active.

However due to ARB_gl_spirv where name reflection information is not
mandatory, we can use the UBO/SSBO binding and variable offset to
filter which variables which are active.

v2: use RESOURCE_UBO/UNI macros instead of direct castings, update
    comment (Alejandro)

v3: Change signature of _mesa_program_resource_find_active_variable
    to simplify calling it. Also, squash the fix for find_binding_offset
    for arrays of blocks (Arcady)

Signed-off-by: Antia Puentes <apuentes@igalia.com>
Signed-off-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: Arcady Goldmints-Orlov <agoldmints@igalia.com>

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-07-12 23:42:41 +02:00
Antia Puentes
161de77e0f mesa/shader_query: Fix LOCATION_INDEX query (ARB_gl_spirv)
When querying GL_LOCATION_INDEX using glGetProgramResourceiv
we already know the index of the resource, we do not need to find
it using the name, which is convenient for shaders coming from
SPIR-V binaries where names are optional.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-07-12 23:42:41 +02:00
Antia Puentes
8818553f18 mesa/shaderapi: Fix TRANSFORM_FEEDBACK_VARYING program query
Fixes the program queries API (glGetProgramiv):
TRANSFORM_FEEDBACK_VARYINGS and TRANSFORM_FEEDBACK_VARYING_MAX_LENGTH
in two cases:

  1. ARB_enhaced_layouts:

The queries were not working for GLSL shaders which specify the
varyings using enhanced layouts. We were returning the info as if the
varyings could only be specified using the API.

  2. ARB_gl_spirv:

TRANSFORM_FEEDBACK_VARYING_MAX_LENGTH should return 1 if there is no
name reflection information available.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-07-12 23:42:41 +02:00
Antia Puentes
8792abff9d mesa/uniforms: Fix GetUniformLocation (ARB_gl_spirv)
From the ARB_gl_spirv specification, glGetUniformLocation should
return -1 when no name reflection is available.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-07-12 23:42:41 +02:00
Antia Puentes
96d6156678 mesa/shader_query: Fix NAME_LENGTH queries (ARB_gl_spirv)
For shaders constructed from SPIR-V binaries, it is possible that
no name reflection information is available. In that case,

 - glGetProgramInterfaceiv(.., pname=MAX_NAME_LENGTH, ..)
 - gletProgramResourceiv(.., props=NAME_LENGTH, ..)

should return 1.

Signed-off-by: Antia Puentes <apuentes@igalia.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-07-12 23:42:41 +02:00
Alejandro Piñeiro
3ebd60b491 mesa: Fix ACTIVE_*_MAX_LENGTH program queries (ARB_gl_spirv)
Since ARB_gl_spirv it is possible to miss a lot of name reflection
information, so it is needed to add NULL name checks for several
queries, and return a specific value on those cases. This commit add
them for ACTIVE_UNIFORM_BLOCK_MAX_NAME_LENGTH,
ACTIVE_ATTRIBUTE_MAX_LENGTH and ACTIVE_UNIFORM_MAX_LENGTH.

From ARB_gl_spirv spec:

   "If pname is ACTIVE_UNIFORM_BLOCK_MAX_NAME_LENGTH, the length of
    the longest active uniform block name, including the null
    terminator, is returned. If no active uniform blocks exist, zero
    is returned. If no name reflection information is available, one
    is returned.

    If pname is ACTIVE_ATTRIBUTE_MAX_LENGTH, the length of the longest
    active attribute name, including a null terminator, is returned.
    If no active attributes exist, zero is returned. If no name
    reflection information is available, one is returned.

    If pname is ACTIVE_UNIFORM_MAX_LENGTH, the length of the longest
    active uniform name, including a null terminator, is returned. If
    no active uniforms exist, zero is returned. If no name reflection
    information is available, one is returned."

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-07-12 23:42:41 +02:00
Antia Puentes
cafc1a40d4 nir/types: Add glsl_type_is_unsized_array helper
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-07-12 23:42:41 +02:00
Antia Puentes
bfc5e46746 nir/linker: Fill TOP_LEVEL_ARRAY_SIZE and STRIDE
From the ARB_program_interface_query specification:

    "For the property TOP_LEVEL_ARRAY_SIZE, a single integer
    identifying the number of active array elements of the top-level
    shader storage block member containing to the active variable is
    written to <params>.  If the top-level block member is not
    declared as an array, the value one is written to <params>.  If
    the top-level block member is an array with no declared size, the
    value zero is written to <params>."

    "For the property TOP_LEVEL_ARRAY_STRIDE, a single integer
    identifying the stride between array elements of the top-level
    shader storage block member containing the active variable is
    written to <params>.  For top-level block members declared as
    arrays, the value written is the difference, in basic machine
    units, between the offsets of the active variable for consecutive
    elements in the top-level array.  For top-level block members not
    declared as an array, zero is written to <params>."

v2: move top_level_array_size and stride into nir_link_uniforms_state
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-07-12 23:42:41 +02:00
Antia Puentes
ae2ea5ec1f nir/linker: Compute the offset for non-trivial uniform types.
ARB_gl_spirv points that the offset must be explicit, however this is
true for 'root' types. For complex types, like struct members or
arrays of arraya, it needs to be computed.

We are not using the offset stored in the gl_buffer_variables during
the uniform blocks linking because currently we do not have a way to
relate a gl_buffer_variable with its corresponding gl_uniform_storage.
The GLSL path uses the name for that, but we can not rely on that
because names are optional in SPIR-V.

Notice that uniforms non-backed by a buffer object will have an offset
equal to -1, like in the GLSL path.

v2: add offset and var_is_in_block as per-variable state in
    nir_link_uniforms_state (Arcady)

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-07-12 23:42:41 +02:00
Antia Puentes
e15c663d8e nir/linker: Add atomic counters to the program resource list
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-07-12 23:42:41 +02:00
Antia Puentes
e1464a1cf8 nir/linker: Add XFB resources to the program resource list
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-07-12 23:42:41 +02:00
Antia Puentes
53087a89ac nir/linker: Add BUFFER_VARIABLEs to the prog resource list
v2: use link_util_should_add_buffer_variable() (Arcady)
Signed-off-by: Arcady Goldmints-Orlov <agoldmints@igalia.com>

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-07-12 23:42:41 +02:00
Antia Puentes
ffdb44d3a0 nir/linker: Add inputs/outputs to the program resource list
v2: added TODO comment hinting possible future refactoring of
    nir_build_program_resource_list and build_program_resource_list,
    to avoid code duplication (Alejandro, to explicitly reflect a
    valid concern from Timothy during the review).

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-07-12 23:42:41 +02:00
Alejandro Piñeiro
691cee751a nir/linker: add ubo/ssbo to the program resource list
v2: "nir/linker: Use the stageref when adding UBO/SSBO resources"
     squashed on this one (Timothy)

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-07-12 23:42:41 +02:00
Antia Puentes
a638971929 nir/linker: Fill the uniform's BLOCK_INDEX
Binding comparison is used to determine the block the uniform is part
of. Note that to do the binding comparison we need the information in
UniformBlocks[] and ShaderStorageBlocks[] to be available, so we have
to call gl_nir_link_uniform_blocks() before linking the uniforms.

v2: add missing break (Timothy)

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-07-12 23:42:41 +02:00
Samuel Pitoiset
f239e22813 radv/gfx10: enable 1D textures
Mirror RadeonSI. This also fixes crashes in addrlib.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-12 18:25:45 +02:00
Andres Gomez
f4d2be03b1 intel/compiler: remove abandoned comments
c8665005: ("intel/compiler: Don't always require precise lowering of flrp")
forgot to remove some comments that didn't apply any more after the
change.

Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrnd.net>
2019-07-12 16:15:20 +00:00
Andres Gomez
9aadd5d688 nir/compiler: keep same bit size when lowering with flrp
This was probably not caught before because no supported test was
exercising the flrp lowering with other bit size different than 32.

With the arrival of VK_KHR_shader_float_controls we will have some of
those and, unless we keep the bit size, we will end with something
like:

../src/compiler/nir/nir_builder.h:420: nir_builder_alu_instr_finish_and_insert: Assertion `src_bit_size == bit_size' failed.

Fixes: 158370ed2a ("nir/flrp: Add new lowering pass for flrp instructions")
Fixes: ae02622d8f ("nir/flrp: Lower flrp(a, b, c) differently if another flrp(_, b, c) exists")
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrnd.net>
2019-07-12 16:15:20 +00:00
Jason Ekstrand
16842b2391 anv: Properly compute image usage in CreateImageView
With separate stencil usage, we can't just grab the usage from the image
directly and have to consider the per-aspect usage instead.

Fixes: 1be38f9178 "anv:Use VK_EXT_separate_stencil_usage to avoid..."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-07-12 16:13:48 +00:00
Samuel Pitoiset
b393b2ce95 radv/gfx10: emit DISABLE_CONSERVATIVE_ZPASS_COUNTS
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-12 17:47:12 +02:00
Samuel Pitoiset
8cc4e4a81e radv/gfx10: init more registers in the graphics preamble
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-12 17:47:12 +02:00
Samuel Pitoiset
e68b55f5e3 radv/gfx10: set HS/GS/CS.WGP_MODE
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-12 17:47:12 +02:00
Samuel Pitoiset
5d5e26230a radv/gfx10: emit GE_PC_ALLOC
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-12 17:47:11 +02:00
Samuel Pitoiset
df062afa03 radv/gfx10: enable vertex shaders without export parameters
GFX10 allows this.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-12 17:47:11 +02:00
Samuel Pitoiset
3f76c0f47c radv/gfx10: launch 2 compute waves per CU before going onto the next CU
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-12 17:47:11 +02:00
Samuel Pitoiset
e631d65fc6 radv: use ac_get_compute_resource_limits()
No behaviour change.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-12 17:47:11 +02:00
Samuel Pitoiset
e510c5ee3b ac: import ac_get_compute_resource_limits() from RadeonSI
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-12 17:47:11 +02:00