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radv: use ac_get_compute_resource_limits()
No behaviour change. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
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1 changed files with 6 additions and 17 deletions
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@ -4378,8 +4378,9 @@ radv_compute_generate_pm4(struct radv_pipeline *pipeline)
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{
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struct radv_shader_variant *compute_shader;
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struct radv_device *device = pipeline->device;
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unsigned compute_resource_limits;
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unsigned threadgroups_per_cu = 1;
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unsigned waves_per_threadgroup;
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unsigned max_waves_per_sh = 0;
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uint64_t va;
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pipeline->cs.buf = malloc(20 * 4);
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@ -4405,24 +4406,12 @@ radv_compute_generate_pm4(struct radv_pipeline *pipeline)
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DIV_ROUND_UP(compute_shader->info.cs.block_size[0] *
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compute_shader->info.cs.block_size[1] *
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compute_shader->info.cs.block_size[2], 64);
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compute_resource_limits =
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S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
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if (device->physical_device->rad_info.chip_class >= GFX7) {
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unsigned num_cu_per_se =
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device->physical_device->rad_info.num_good_compute_units /
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device->physical_device->rad_info.max_se;
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/* Force even distribution on all SIMDs in CU if the workgroup
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* size is 64. This has shown some good improvements if # of
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* CUs per SE is not a multiple of 4.
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*/
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if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
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compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
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}
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radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
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compute_resource_limits);
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ac_get_compute_resource_limits(&device->physical_device->rad_info,
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waves_per_threadgroup,
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max_waves_per_sh,
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threadgroups_per_cu));
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radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
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radeon_emit(&pipeline->cs,
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