MOV_INDIRECT picks one lane from the src[0] and moves it to all lanes
in the destination. Even if we split the instruction, src[0] should
remain identical.
Noticed this while trying to use this instruction in SIMD32. All
current use cases are limited to SIMD8 shaders (or SIMD16 on Xe2). Or
maybe in SIMD32 but with a uniform src[0]. That's we think we've never
seen the issue so far.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28036>
if mesh and task shaders are bound separately, and if they have different
workgroup sizes, the setting of workgroup size will be broken if
set during shader bind
this must be deferred to draw time to pull the correct values
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29733>
Turns out the current approach makes implementation of advanced features
like update-after-bind or shader modules quite challenging. Instead of
adding hacks all over the place to support these features, let's use
the Valhall descriptor model.
Each shader now gets its own descriptor tables, which are fed by pilot
shaders copying the descriptors used by the shader from the descriptor
sets currently bound the command buffer.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Co-developped-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29654>
The Bifrost descriptor model is a dead end for advanced features like
shader modules, pipeline libraries or update-after-bind. Let's prepare
the Valhall implementation so we can re-use it on Bifrost.
The implementation itself was pretty generic already. We just need to
map image descriptors to AttributeBuffer instead Texture descriptors,
and the Buffer object had no equivalent on Bifrost, so we just use a
software-defined panvk_ssbo_addr object containing the SSBO address and
size, and make sure this object is padded to 32-bytes.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29654>
Valhall descriptor model was loosely based on the Vulkan descriptor
model. Provide a new implementation for the VkDescriptor{Set,Pool}
objects that matches this new model.
Co-developed-by: Mary Guillemard <mary.guillemard@collabora.com>
Co-developed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29654>
Valhall descriptor model was loosely based on the Vulkan descriptor
model. Provide a new implementation for the VkDescriptorSetLayout
object that matches this new model.
Co-developed-by: Mary Guillemard <mary.guillemard@collabora.com>
Co-developed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29654>
Valhall (v9/v10) will be added progressively. In order to allow that,
we need to extend the panvk_per_arch() macro for v9/v10 and tweak
meson.build so it does include valhall sources without compiling
common per-arch files.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29654>
The only difference here is the fact image attributes are gone, and
texture descriptors are used instead. We rework the code so it uses
panfrost_new_texture() to emit the texture/plane descriptors, which
leaves us with one less thing to worry about.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29654>
There's no image attribute on Valhall, storage images are passed as
texture descriptors.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29654>
The shifted offsets generated by ir3_nir_lower_io_offsets are not always
optimized well by nir_opt_offsets. If the offset to be shifted has the
form "iadd constant, foo" don't shift the result but transform it to
"iadd constant>>shift, (ushr foo, shift)". This ensures nir_opt_offsets
(which only looks for iadds) can fold the constant into the immediate
offset.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28664>
On some ISAs (e.g., ir3) the offset calculation wraps the same way as
normal unsigned addition so potentially wrapping operations do not have
to be ignored.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28664>
To support cases where different instructions may be used for the same
storage type. For example, to load from an SSBO on ir3, either ldib (max
offset 127) or isam.v (max offset 255) can be used.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28664>
Add the BASE index to the load/store_ssbo_ir3 intrinsic to store an
immediate offset. This offset is encoded in the corresponding fields of
isam.v/ldib.b/stib.b.
One extra optimization is implemented: whenever the regular offset is
also a constant, the total offset (regular plus immediate) is aligned
down to a multiple of the max immediate offset and this is used as the
regular offset while the immediate is set to the remainder. This ensures
that the register used for the regular offset can often be reused among
multiple contiguous accesses.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28664>
Since a7xx, isam.v can be used to perform multi-component SSBO loads.
Use this whenever possible to prevent excessive scalarization. isam.v
also uses only a single coordinate (as opposed to a 2-dimensional
coordinate for isam) so this reduces register pressure as well.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28664>
isam.v is a version of isam that can load multiple components from IBOs.
It uses some bits that are used for different purposes in other tex
instructions:
- bit 50 (.v): .s elsewhere
- bit 53 (indicates whether an immediate offset is used): .p elsewhere
- bit 18 (.1d when not set, has to be set for .v): 0 elsewhere
For this reason, the bitset hierarchy for cat5 had to be reordered a
bit.
The immediate offset is encoded as an extra (immed) source register and
an instruction flag (to be able to make the distinction between offset
zero and no offset, although this might not be useful).
This also adds a flag for the .1d field. Since this bit is active-low,
this flag has inverted semantics: setting it will make .1d inactive.
Note that some existing disassembler tests for isam had to be updated
because the bit is never set and this is now disassembled as .1d. This
matches the blob's disassembler.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28664>
Rebasing around this patch has been a significant burden for development.
Staging patches to asahi/mesa helps somewhat but 1. it's still really
frustrating to have this much divergence with upstream, and 2. ideally we
wouldn't have to do that.
The kernel upstreaming is stalled for various reasons. This patch adds
compile-only code to speak the unstable Linux UAPI for the SOLE purpose of
reducing my rebase pain... NOT to actually work.
It is NOT for users OR distro maintainers. asahi will refuse to probe on
upstream Mesa to protect against regressions. The uapi is NOT STABLE and
upstream Mesa CANNOT be used with it. Attempting to bypass this WILL give you a
broken system.
This patch employs several layers of deterrents against system-breaking
enablement. With a lot of warning text at the relevant sites. Hopefully that is
good enough to prevent people from breaking systems. And if people brazenly
ignore all of the above ... they get to pick up the pieces.
You have been warned.
---
There is significant prior art for Mesa including downstream kernel uapi
supports in-tree:
* powervr (downstream android driver)
* turnip (downstream kgsl android driver)
* asahi ... ironically (prop macOS kernel driver)
* maybe vc4?
Linux is only special because of distros shipping tagged Mesa releases. The
several layers of guards here guarantee that no tagged Mesa release would
possibly probe even on an asahi downstream kernel. A distro would need a
significant scary patch to make it probe. If/when it breaks, that's on them
and they pick up the pieces.
I make a stability guarantee ONLY for Fedora Asahi Remix -- where we push
packages for both a downstream kernel and Mesa in tandem, while we patiently
wait for upstreaming -- and that is *it*. It will be a nice future when this all
works upstream, but unfortunately we're not there yet.
Acked by Dave [1] and Sima [2]
[1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29620#note_2444189
[2] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29620#note_2445155
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Co-developed-by: Asahi Lina <lina@asahilina.net>
Signed-off-by: Asahi Lina <lina@asahilina.net>
Co-developed-by: Sergio Lopez <slp@sinrega.org>
Signed-off-by: Sergio Lopez <slp@sinrega.org>
Co-developed-by: i509VCB <git@i509.me>
Signed-off-by: i509VCB <git@i509.me>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29620>
This gets rid of most of the pointless bitfields and also moves away from
unsigned, which we really should stop using :)
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29720>
This allows for a more strongly typed field on the Rust side.
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29720>
This works around a bindgen bug, but also moves the value into a single
byte as per the addition of compression_rate it spanned over two bytes.
Fixes: 5db7398672 ("gallium: add interface for fixed-rate surface/texture compression")
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29720>
Having zero consts in one FS may corrupt consts in follow up FSs,
on such GPUs blob never has zero consts in FS. The mechanism of
corruption is unknown.
Fixes geometry flickering in a number of games, including:
Baldur's Gate 3
Assasin's Creed Rogue
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29357>
Copying UBWC image via BLIT_OP_SCALE may be corrupted if previously
someone copied image with bit 18 set in TPL1_DBG_ECO_CNTL1.
Found by replaying blob's cmdstream on a740, but somehow this issue
doesn't happen on Android.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29358>
The job duration is printed during the test progress. It can be collected and
summarized at the end of the process. It is interesting when doing a stress
test as one will have this information together at the end.
Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29419>
Avoids adding back the code after every header update.
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29621>
If we have an array of multi-planar descriptors, buffer_list was
incorrectly incremented and this could have overwritten some BO entries.
In practice, this situation should be very rare because most of the
applications enable the global BO list.
Cc: mesa-stable
Closes: #10559
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28816>
