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freedreno/a7xx: Update TPL1_DBG_ECO_CNTL1 to fix UBWC corruption

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Copying UBWC image via BLIT_OP_SCALE may be corrupted if previously
someone copied image with bit 18 set in TPL1_DBG_ECO_CNTL1.

Found by replaying blob's cmdstream on a740, but somehow this issue
doesn't happen on Android.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29358>
This commit is contained in:
Danylo Piliaiev 2024-05-21 15:09:43 +02:00 • committed by Marge Bot
parent 44e6850016
commit 98e3b1bc5f
2 changed files with 9 additions and 4 deletions
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6
src/freedreno/common/freedreno_devices.py
View file

@ -854,7 +854,7 @@ a730_magic_regs = dict(
a730_raw_magic_regs = [
[A6XXRegs.REG_A6XX_UCHE_CACHE_WAYS, 0x00840004],
[A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x00000724],
[A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x00040724],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE08, 0x00002400],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE09, 0x00000000],
@ -969,7 +969,7 @@ add_gpus([
),
raw_magic_regs = [
[A6XXRegs.REG_A6XX_UCHE_CACHE_WAYS, 0x00040004],
[A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x00000724],
[A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x00040724],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE08, 0x00000400],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE09, 0x00430800],
@ -1055,7 +1055,7 @@ add_gpus([
),
raw_magic_regs = [
[A6XXRegs.REG_A6XX_UCHE_CACHE_WAYS, 0x00040004],
[A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x00000700],
[A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x00040700],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE08, 0x00400400],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE09, 0x00430820],

7
src/freedreno/registers/adreno/a6xx.xml
View file

@ -5884,7 +5884,12 @@ to upconvert to 32b float internally?
<!-- always 0x100000 or 0x1000000? -->
<reg32 offset="0xb600" name="TPL1_DBG_ECO_CNTL" low="0" high="25" usage="cmd"/>
<reg32 offset="0xb601" name="TPL1_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
<reg32 offset="0xb602" name="TPL1_DBG_ECO_CNTL1" usage="cmd"/>
<reg32 offset="0xb602" name="TPL1_DBG_ECO_CNTL1" usage="cmd">
<!-- Affects UBWC in some way, if BLIT_OP_SCALE is done with this bit set
and if other blit is done without it - UBWC image may be copied incorrectly.
-->
<bitfield name="UBWC_WORKAROUND" pos="18" type="boolean"/>
</reg32>
<reg32 offset="0xb604" name="TPL1_NC_MODE_CNTL">
<bitfield name="MODE" pos="0" type="boolean"/>
<bitfield name="LOWER_BIT" low="1" high="2" type="uint"/>