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Author SHA1 Message Date
Maciej Cencora
0aed44f8a3 r600: align to r300 changes in the blit code 
Pitch here means aligned width, not aligned width * bpp.
 2010-01-19 23:38:34 +01:00
Maciej Cencora
0174dac5f3 r300/r600: move some bo offsets checking to blit code 
In preperation for texcopy code sharing.
 2010-01-19 23:38:34 +01:00
Maciej Cencora
ac8afd401f r600: prepare for some code sharing 2010-01-19 23:38:34 +01:00
Maciej Cencora
f54e96c597 r300: check if blitting for given format is supported earlier 
Prevents failing assertions at later stage.
 2010-01-19 23:38:33 +01:00
Maciej Cencora
acac99e35a r300: use nearest texture filtering for accelerated blits 2010-01-19 23:38:33 +01:00
Maciej Cencora
f2fea26269 r300: fix Y coord flipping in accelerated blits 2010-01-19 23:38:33 +01:00
Maciej Cencora
11affafc75 radeon: use mesa provided _mesa_tex_target_to_face function 2010-01-19 23:38:33 +01:00
Maciej Cencora
9363a813f1 r300: prepare for texcopy code sharing 2010-01-19 23:38:33 +01:00
Maciej Cencora
f542fde77e radeon: add blit function to vtbl 2010-01-19 23:38:09 +01:00
Eric Anholt
8f7dfe3025 intel: Remove dead note_fence vtbl hook. 2010-01-19 12:09:29 -08:00
Eric Anholt
a45f24c0a4 i965: Improve the hashing of brw_state_cache keys to include the cache_id. 
No measurable difference on cairoperf.
 2010-01-19 11:35:33 -08:00
Eric Anholt
d1cefabf98 i965: Remove obsolete comment about the state atoms. 2010-01-19 11:32:57 -08:00
Eric Anholt
fb4901593c i965: Upload as many VS constants as possible through the push constants. 
The pull constants require sending out to an overworked shared unit
and waiting for a response, while push constants are nicely loaded in
for us at thread dispatch time.  By putting things we access in every
VS invocation there, ETQW performance improved by 2.5% +/- 1.6% (n=6).
 2010-01-19 11:31:23 -08:00
Eric Anholt
62a96f74c9 i965: Allow for variable-sized auxdata in the state cache. 
Everything has been constant-sized until now, but constant buffer
handling changes will make us want some additional variable sized
array.
 2010-01-19 11:31:05 -08:00
Eric Anholt
7d4e674b21 intel: Use the new DRI2 flush invalidate entrypoint to signal frame done. 
Previously for frame throttling we would wait on the first batch after
a swap before emitting another swap, because we had no hook after a
swap was emitted.  This meant that if an app managed to squeeze
everything it for a frame had into one batch, it would lock-step with
the GPU.  With the swapbuffers changes, we now have the entrypoint we
want.

This takes the WoW intro screen from 25% GPU idle and visibly jerky to
4-5% GPU idle and rather smooth.  Other apps such as OpenArena have
run into this problem as well.
 2010-01-19 11:07:51 -08:00
Alan Coopersmith
a7aaf052f9 Sun compilers now support some gcc __attribute__ values 
Sun cc 5.9 and later (__SUNPRO_C >= 0x590) support __attribute__ calls
for aligned, always_inline, noinline, pure, const, and malloc.

This commit includes updates to files that were regenerated by gl_XML.py
after adding the __SUNPRO_C checks to it

Signed-off-by: Alan Coopersmith <alan.coopersmith@sun.com>
Signed-off-by: Brian Paul <brianp@vmware.com>
 2010-01-19 10:15:55 -08:00
Alan Coopersmith
adda7f3215 Check if gcc supports -fvisibility=hidden before adding to CFLAGS 
Signed-off-by: Alan Coopersmith <alan.coopersmith@sun.com>
 2010-01-19 10:15:55 -08:00
Brian Paul
aec3fe82e4 softpipe: remove redundant assignments 
We initialized width/height/depth from pt->width0/height0/depth0 above.
 2010-01-19 11:14:00 -07:00
Alex Deucher
ef631104d5 r100/r200/r600: fix typo in 2b1d5ea4f0 2010-01-19 01:47:04 -05:00
Alex Deucher
2b1d5ea4f0 r100/r200/r600: check if blitting for given format is supported earlier 
based on Maciej's r300 patch.
 2010-01-19 01:42:41 -05:00
Alex Deucher
a67cd1994f r100/r200: add blit support for ARGB4444 2010-01-19 01:26:35 -05:00
Alex Deucher
f6d529083f r60: Add relocs for CB_TILE/FRAG 
as per 46dc6fd3ed
 2010-01-18 22:00:05 -05:00
Corbin Simpson
09f69b1e5d docs: Clarify PIPE_TEXTURE_USAGE_DYNAMIC. 2010-01-18 18:06:55 -08:00
Corbin Simpson
f90733c116 docs: Use proper XOR symbol. 2010-01-18 18:06:55 -08:00
Alex Deucher
daccc962a1 r100: add blit support 
Only enabled with KMS.
 2010-01-18 20:56:58 -05:00
Alex Deucher
1ced546577 r200: add blit support 
Only enabled with KMS.
 2010-01-18 20:56:58 -05:00
Corbin Simpson
047719182f docs: Spacing in TGSI formulae. 
Some of those still look atrocious. :T
 2010-01-18 17:31:56 -08:00
Corbin Simpson
28fd246634 docs: Grammar and refs in Rasterizer. 2010-01-18 17:17:09 -08:00
Corbin Simpson
2598f00078 docs: Cleanup Rasterizer a bit. 
I'm getting better at this, I think.
 2010-01-18 17:12:13 -08:00
Corbin Simpson
2b4ad02321 docs: Fix terms and refs. 
I fail at Sphinx-style ReST.
 2010-01-18 16:40:39 -08:00
Corbin Simpson
4f52dfeda2 docs: Slowly keep fleshing out more info. 2010-01-18 15:30:28 -08:00
Corbin Simpson
9811ebf61f docs: PIPE_TEXTURE_USAGE info. 
From IRC with Jakob.
 2010-01-18 15:30:28 -08:00
Eric Anholt
0714474ae2 i965: Clean up constbuf handling by splitting reladdr/non-reladdr loads. 
The codepaths in the function were almost entirely different.
 2010-01-18 13:52:47 -08:00
Eric Anholt
c653f5f387 i965: Only set up the stack register if it's going to get used. 2010-01-18 13:52:47 -08:00
Eric Anholt
d5b964234c i965: Fix loads of non-relative-addr constants after a reladdr load. 
Fixes piglit vp-arl-constant-array-huge-overwritten.
 2010-01-18 13:52:47 -08:00
Christoph Bumiller
c6559b7e01 nv50: fix constant vtxattr methods 
This function was untested, sorry.
 2010-01-18 21:40:30 +01:00
Christoph Bumiller
0d6e3dd84d nv50: make instanced drawing work with edge flags 
And fix some obvious mistakes introduced in the
previous instancing commit.
 2010-01-18 19:53:29 +01:00
Christoph Bumiller
e74db4f20f nv50: cannot exit shaders on a control flow instruction 
Fixes lockup triggered by this ingenious shader:
   1: CALL :3
   2: END
   3: BGNSUB ...
 2010-01-18 19:53:29 +01:00
Marcin Slusarz
9fb9c9f9ca nv50: fix nv50_program->immd memory leak 2010-01-18 19:53:29 +01:00
Michal Krol
7472cd0f1f tgsi: Fix behaviour of dimension index. 
The dimension index always addresses the second-dimension axis.
 2010-01-18 19:13:49 +01:00
Michal Krol
463351ea6c tgsi: Allow TEMPORARY registers as indirect address into source operands. 2010-01-18 19:13:45 +01:00
Michal Krol
4698a865e0 tgsi: Add ureg_DECL_immediate_block_uint(). 
Allows declaring a contiguous block of immediates. Useful for
relative indexing.
 2010-01-18 19:13:42 +01:00
Brian Paul
4c041fac96 glsl: remove __inline directive 
It makes no difference with gcc -O3, for example.
 2010-01-18 11:06:57 -07:00
Brian Paul
0766780a98 st/mesa: updated comments and whitespace 2010-01-18 10:43:33 -07:00
Marcin Slusarz
e5347ca94d st/mesa: fix memory leak in st_translate_mesa_program 
Signed-off-by: Brian Paul <brianp@vmware.com>
 2010-01-18 10:39:27 -07:00
Alex Deucher
3310fe0e91 r600: fix some warnings 2010-01-18 11:21:19 -05:00
Jerome Glisse
1560183536 r600: Update default state size to account for the new relocation 
the new relocation for CB_COLOR0_FRAG & CB_COLOR0_TILE add 4
dwords to the default command stream. Increase the prediction
default size to take this into account
 2010-01-18 15:32:24 +01:00
Jerome Glisse
46dc6fd3ed r6xx/r7xx: emit relocation for FRAG & TILE buffer 
FRAG & TILE buffer are unused but still they need
to be associated with a valid relocation so that
userspace can't try to abuse them to overwritte
GART and then try to write anywhere in system
memory.
 2010-01-18 12:14:07 +01:00
Andre Maasikas
7b82f0f67e r600: fix shadow_ambient shader 
rtype enums are different, DST_REG_OUTPUT got SRC_REG_CONSTANT in some
shaders and produced invalid output/hang
as TEX output is temp register always set out src to SRC_REG_TEMPORARY
 2010-01-18 12:49:06 +02:00
Corbin Simpson
0857f38c39 radeong: Don't allocate HW BOs for constantbufs. 
We have broken 1000 FPS. Hell yes.

Heavily inspired by Marek's patch, but using pipebuffer instead of
a roll-your-own malloc.
 2010-01-18 02:35:08 -08:00