Commit graph

99109 commits

Author SHA1 Message Date
Grazvydas Ignotas
047c6fe2c5 r300g: remove double assignment
Trivial. Found by Coccinelle.
2018-01-14 23:04:49 +02:00
Grazvydas Ignotas
6acf22a179 util: use faster zlib's CRC32 implementaion
zlib provides a faster slice-by-4 CRC32 implementation than the
traditional single byte lookup one used by mesa. As most supported
platforms now link zlib unconditionally, we can easily use it.

Improvement for a 1MB buffer (avg MB/s, n=100, zlib 1.2.8):

  i5-6600K                    C2D E4500
mesa zlib                    mesa zlib
 443 1443 225% +/- 2.1%       403 1175 191% +/- 0.9%

It has been verified the calculation results stay the same after this
change.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2018-01-14 19:10:33 +02:00
Grazvydas Ignotas
87f723408b android,configure,meson: define HAVE_ZLIB
The next change wants to use some optional zlib functionality, however
not all platforms currently use zlib. Based on earlier Jordan Justen's
patches and their review feedback.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2018-01-14 18:52:23 +02:00
Grazvydas Ignotas
b7347cc313 util/crc32: don't drop the const qualifier
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2018-01-14 18:47:50 +02:00
Timothy Arceri
e6378962ce ac: add doubles support to isign
Fixes a number of int64 piglit tests, for example:

generated_tests/spec/arb_gpu_shader_int64/execution/built-in-functions/fs-sign-i64vec2.shader_test

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-01-14 11:40:03 +11:00
Timothy Arceri
38876c88d1 ac: add i64_0 and i64_1 to llvm build context
These will be used in the following patch.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-01-14 11:40:03 +11:00
Timothy Arceri
741b21b713 ac/nir: fix translation of nir_op_b2i for doubles
V2: just zero-extend the 32-bit value.

Fixes a number of int64 piglet tests, for example:

generated_tests/spec/arb_gpu_shader_int64/execution/conversion/frag-conversion-explicit-bool-int64_t.shader_test

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-01-14 11:40:03 +11:00
Mauro Rossi
4d61eb8018 ac: fix build error in si_shader
assert() is replaced by unreachable(), to avoid following building error:

external/mesa/src/gallium/drivers/radeonsi/si_shader.c:1967:1:
error: control may reach end of non-void function [-Werror,-Wreturn-type]
}
^
1 error generated.

Fixes: c797cd6 ("ac: add load_patch_vertices_in() to the abi")

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-01-13 18:13:07 +11:00
Timothy Arceri
f0d74ecce8 radv/radeonsi/nir: lower 64bit flrp
Fixes a bunch of arb_gpu_shader_fp64 piglit tests for example:

generated_tests/spec/arb_gpu_shader_fp64/execution/built-in-functions/fs-mix-double-double-double.shader_test

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-01-13 18:04:40 +11:00
Eric Anholt
5bc0b63799 broadcom/vc5: Use MSF to ignore discards/non-dispatched channels in loops.
Prevents potential infinite loops when a non-dispatched or discarded
channel never triggers the loop break condition.
2018-01-12 21:58:24 -08:00
Eric Anholt
762dd52951 broadcom/vc5: Use XOR instead of SUB for execute flags comparisons.
I think this should be equivalent other than power, and it's the kind of
comparison we use for nir_op_ieq.
2018-01-12 21:58:18 -08:00
Eric Anholt
8e4cba9d92 broadcom/vc5: Also check the update flags for avoiding DCE.
I was trying to do a NULL-destination UF, and it got removed.
2018-01-12 21:58:11 -08:00
Eric Anholt
ff77ca8a3b broadcom/vc5: Fix up channel swizzling for textures on 4.x.
I had 3.x putting swizzling in the texture state only for 16-bit texture
returns, and in the shader for 32-bit.  This may be due to having mixed up
the return channel setup on 3.x back before I had moved it into the
compiler.  On 4.x, the non-border-color texwrap tests are passing nicely
with both 16 and 32-bit returns with swizzling in the texture state.
2018-01-12 21:58:04 -08:00
Eric Anholt
e41e33fdb8 broadcom/vc5: Port the draw-time state emission to V3D 4.1. 2018-01-12 21:57:52 -08:00
Eric Anholt
aa77a9cf5a broadcom/vc5: Rename V3D 3.x Flat Shade Action to match v4.x naming.
Now that the actions are reused for centroid and nonperspective, give them
a more generic name.
2018-01-12 21:57:45 -08:00
Eric Anholt
8e4c705515 broadcom/vc5: Update pixel center setup for V3D 4.x.
The fxcd/fycd instructions now return half-integer pixel centers when not
doing sample-rate shading.
2018-01-12 21:57:37 -08:00
Eric Anholt
95873a184e broadcom/vc5: Print the buffer name in simulator overflow checks.
Revealed that I was writing past the TSDA, not the Z buffer as I expected.
2018-01-12 21:57:30 -08:00
Eric Anholt
368bab43fd broadcom/vc5: Add support for loading varyings in V3D 4.1.
The LDVARY signal now writes an arbitrary register, so I took out the
magic src register file and replaced it with an instruction with LDVARY
set so we have somewhere to hang a QFILE_TEMP destination for register
allocation.
2018-01-12 21:57:21 -08:00
Eric Anholt
af9753e246 broadcom/vc5: Update state setup for V3D 4.1. 2018-01-12 21:57:09 -08:00
Eric Anholt
5aaea3c4a0 broadcom/vc5: Add compiler support for V3D 4.x texturing. 2018-01-12 21:56:57 -08:00
Eric Anholt
028f6b327c broadcom/vc5: Add the new TMU write addresses for V3D 4.x (and r5rep).
The V3D 3.x series of TMU writes with meaning depending on the texture
type is replaced with writes to specific registers for each texture
argument semantic.
2018-01-12 21:56:48 -08:00
Eric Anholt
42a35da96d broadcom/vc5: Move V3D 3.3 texturing to a separate file.
V3D 4.x texturing changes enough that #ifdefs would just make a mess of
it.
2018-01-12 21:56:37 -08:00
Eric Anholt
acf30e4916 broadcom/vc5: Move V3D 3.3 VPM write setup to a separate file.
For V4.1 texturing, I need the V4.1 XML, so the main compiler needs to
stop including V3.3 XML.
2018-01-12 21:56:24 -08:00
Eric Anholt
725d73981a broadcom/vc5: Set up depth formats for V3D 4.x.
We no longer have the small depth-specific output format enum, and instead
depth is just at the end of the output image format enum.
2018-01-12 21:56:17 -08:00
Eric Anholt
66f2f3ed97 broadcom/vc5: Always use the RGBA8 formats for RGBX8.
The RGBX8 formats were dropped from V3D 4.x, but we don't really need them
anyway (we already handle other non-alpha formats by forcing A to 1).
2018-01-12 21:56:10 -08:00
Eric Anholt
469bbd8387 broadcom/vc5: Move the formats table to per-V3D-version compile. 2018-01-12 21:56:00 -08:00
Eric Anholt
34898c8c45 broadcom/vc5: Add support for V3D 4.1 CLIF dumping. 2018-01-12 21:55:49 -08:00
Eric Anholt
409696b76e broadcom/vc5: Move the body of CLIF dumping to a per-version file.
I want the library's entrypoints to still be unversioned, but the actual
packet dumping needs to be per-version.
2018-01-12 21:55:38 -08:00
Eric Anholt
90269ba353 broadcom/vc5: Use THRSW to enable multi-threaded shaders.
This is a major performance boost on all of V3D, but is required on V3D
4.x where shaders are always either 2- or 4-threaded.
2018-01-12 21:55:30 -08:00
Eric Anholt
86a12b4d5a broadcom/vc5: Properly schedule the thread-end THRSW.
This fills in the delay slots of thread end as much as we can (other than
being cautious about potential TLBZ writes).

In the process, I moved the thread end THRSW instruction creation to the
scheduler.  Once we start emitting THRSWs in the shader, we need to
schedule the thread-end one differently from other THRSWs, so having it in
there makes that easy.
2018-01-12 21:55:23 -08:00
Eric Anholt
a075bb6726 broadcom/vc5: Implement GFXH-1684 workaround.
Apparently the VPM writes need to be flushed out before we end the shader.
2018-01-12 21:55:15 -08:00
Eric Anholt
57965755e2 broadcom/vc5: Port drawing commands to V3D 4.x.
This required extending the CL submit ioctl, because the tile alloc/state
buffer setup has moved from the BCL to register writes.
2018-01-12 21:55:04 -08:00
Eric Anholt
f50d39ab49 broadcom/vc5: Add a test for .ifb in ADD ops.
I had a .ifb being decoded weird in sampid, so this is to check that .ifb
is fine.
2018-01-12 21:54:57 -08:00
Eric Anholt
267f13dbee broadcom/vc5: Add the new tesselation opcodes in V3D 4.1. 2018-01-12 21:54:50 -08:00
Eric Anholt
edbd817c30 broadcom/vc5: Use a physical-reg-only register class for LDVPM.
This is needed for LDVPM on V3D 4.x, but will also be needed for keeping
values out of the accumulators across THRSW.
2018-01-12 21:54:42 -08:00
Eric Anholt
22a02f3e34 broadcom/vc5: Use the new LDVPM/STVPM opcodes on V3D 4.1.
Now, instead of a magic write register for VPM stores we have an
instruction to do them (which means no packing of other ALU ops into it),
with the ability to reorder the VPM stores due to the offset being baked
into the instruction.

VPM loads also gain the ability to be reordered by packing the row into
the A argument.  They also no longer write to the r3 accumulator, and
instead must be stored to a physical register.
2018-01-12 21:54:33 -08:00
Eric Anholt
55f8a01aca broadcom/vc5: Drop dead VC5_QPU_* defines from qpu_instr.c.
I had all the packing code in this file at one point, but these defines
now live in qpu_pack.c.
2018-01-12 21:54:27 -08:00
Eric Anholt
2bd378647b broadcom/vc5: Add support for QPU pack/unpack/disasm of small immediates. 2018-01-12 21:54:18 -08:00
Eric Anholt
5f227ac210 broadcom/vc5: Enable the driver on V3D 4.1 2018-01-12 21:54:12 -08:00
Eric Anholt
39ce1ab7ba broadcom/vc5: Port the simulator to support V3D 4.1
This required moving the register accesses to a separate v3dx file, since
the register definitions for each V3D version collide.  It seems that
initializing the v3d_hw from a file dictating 3.3
(v3d_simulator_wrapper.cpp) is safe, though.
2018-01-12 21:54:00 -08:00
Eric Anholt
c81cc767e4 broadcom/vc5: Drop signal bit #defines.
Signals are more complicated than that, and tables ended up being better.
2018-01-12 21:53:53 -08:00
Eric Anholt
dfee62eed3 broadcom/vc5: Add support for V3Dv4 signal bits.
The WRTMUC replaces the implicit uniform loads in the first two texture
instructions.  LDVPM disappears in favor of an ALU op.  LDVARY, LDTMU,
LDTLB, and LDUNIF*RF now write to arbitrary registers, which required
passing the devinfo through to a few more functions.
2018-01-12 21:53:45 -08:00
Eric Anholt
81ec2ba229 broadcom/vc5: Fix pack/unpack of vfmul input unpack flags. 2018-01-12 21:53:38 -08:00
Eric Anholt
954a704da3 broadcom/vc5: Port the RCL setup to V3D4.1.
The TLB load/store path is rebuilt in this version.  There is no longer a
single-byte resolved store or the 3-byte extended store.  Instead, you get
to always use general loads/stores (which, honestly, was tempting even in
previous versions).
2018-01-12 21:53:26 -08:00
Eric Anholt
80c84241af broadcom/vc5: Fix per-tile extra clear packet.
I accidentally emitted this into the RCL instead of the per-tile generic
list, so we wouldn't get tiles after the first cleared.
2018-01-12 21:52:02 -08:00
Eric Anholt
f13fe510d1 broadcom/vc5: Move the TLB loads and stores to helper functions.
This is going to get more complicated with V3D 4.1 support, which redoes
all the TLB packets.
2018-01-12 21:51:54 -08:00
Eric Anholt
2c48ce74f7 broadcom/vc5: Convert vc5_cl.h to use the V3DX() macros.
To conditionally compile cl_emit() macros per V3D version, we need it to
expand to whatever V3D we're building for.  This required emitting #define
V3D_VERSION 33 in all our currently 3.3-only code.
2018-01-12 21:51:47 -08:00
Eric Anholt
fb4face86a broadcom/vc5: Introduce v3dx_macros.h and v3dx_pack.h headers.
This will be used by vc5 for prefixing functions and including the pack
header in v3d-version-dependent code, following the model of anv.
2018-01-12 21:51:40 -08:00
Eric Anholt
7dedfd9660 broadcom/cle: Fix error path of missing a "type" in the XML.
We try to emit a #error and continue so that you can debug the missing
type at C compile time, but were missing a couple of definitions in that
path (sigh, python).
2018-01-12 21:51:34 -08:00
Eric Anholt
3d8ad50370 broadcom/vc5: Add XML for V3D v4.1 (BCM7278) 2018-01-12 21:48:07 -08:00