Commit graph

219553 commits

Author SHA1 Message Date
Leder, Brendan Steve (Brendan)
4f93449774 amd/vpelib: Add missing JFIF enum
[WHY & HOW]
Currently missing RGB JFIF enum for switch case - add it in
Also updated unit test to pass

Signed-off-by: Brendan Steve Leder <BrendanSteve.Leder@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40210>
2026-03-04 13:16:57 +08:00
Shih, Jude
3b86244d2e amd/vpelib: Gate assertion on debug flag
add debug flag assert_when_not_support condition for
assert

Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Jude Shih <Jude.Shih@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40210>
2026-03-04 13:16:57 +08:00
Ali, Nawwar
264ee40149 amd/vpelib: Move shaper and 3D LUT updates to vpe_color_update_movable_cm
Refactor shaper normalization and 3D LUT initialization logic from
vpe_calculate_shaper() to vpe_color_update_movable_cm() for proper
sequencing. Remove unused vpe_shaper_generator() declaration.

Signed-off-by: Nawwar Ali <nawwar.ali@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40210>
2026-03-04 13:16:57 +08:00
Hsieh, Mike
db51152100 amd/vpelib: Move feature skip after buffer size return
[WHY]
Feature skip should not perform in buffer size return case.

[HOW]
Move feature skip call after checking for none buffer size return case.

Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Mike Hsieh <Mike.Hsieh@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40210>
2026-03-04 13:16:57 +08:00
Agate, Jesse
e270075d50 amd/vpelib: Predication fix
Cmd buffer size and original start adress should be restored after
predication command has been added

Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Jesse Agate <Jesse.Agate@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40210>
2026-03-04 13:16:57 +08:00
Zhao, Jiali
e130e430b7 amd/vpelib: Re-enable new feature support check
[WHY]
Re-enable new feature support check and fix test-item crash bug

[HOW]
move blending support check into num_streams loop, test-item in
num_streams is 0 so that to fix the crash bug.

Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Jiali Zhao <Jiali.Zhao@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40210>
2026-03-04 13:16:57 +08:00
Chan, Roy
f1ff697dbe amd/vpelib: add a new cap to differentiate scaler coeff handling
[Why]
Issue found when playing video with GDS.
The caller doesn't know if external coefficient should be generated or
not.
To match mm shader handling, it was using external coefficients.

New policy is to follow shared scaler handling with DCN.

[How]
- Introduce a new cap to tell if it is preferred to have external
coefficients.
- For Scaling limit, as supporting 6:1 was not conclusive with GDS,
It is going to have the same behavior as before - 4:1

Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Roy Chan <roy.chan@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40210>
2026-03-04 13:16:57 +08:00
Chuanyu Tseng
7d5aeda5ff Revert "amd/vpelib: Adding new wrapper for register profiling"
This reverts commit d42268f3e5.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40210>
2026-03-04 13:15:39 +08:00
Timothy Arceri
73bc604128 glsl: relax precision matching on unused uniforms ES
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0886be09 ("glsl: Allow precision mismatch on dead data with GLSL ES 1.00")
allowed precision mismatches on uniforms, however if you lower precision on
16-bit consts, then this error triggers instead.

So here we relax the type matching and just make sure we match int vs
float.

Fixes: 0886be09 ("glsl: Allow precision mismatch on dead data with GLSL ES 1.00")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5337
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40107>
2026-03-03 22:03:18 +00:00
Rob Clark
78e323c755 ir3: Handle (some) convert_alu_types in backend
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Lower some @convert_alu_types in NIR, preserving the ones that turn into
a single instruction in ir3.

1) Things that turn into a trivial convert (ie. single ALU opc) are
   lowered in nir.
2) Things with 64b src or dst need nir_lower_int64, so those get lowered
   in nir.
3) Things with 8b src or dst turn into multiple cov instructions, so
   lower those in nir.

Everything else that turns into a single cov instruction with various
rounding modes is preserved.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40179>
2026-03-03 12:13:04 -08:00
Rob Clark
dfaa4375c3 rusticl: Let backend control convert_alu_types lowering
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40179>
2026-03-03 12:13:04 -08:00
Rob Clark
b74a07a422 freedreno/a6xx: Avoid touching long lived stateobj refcnt
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In particular, sharable shaders can be used from multiple threads/ctxs,
making the non-atomic refcnting unsound.

But we can avoid making the refcnting atomic just for this one specific
case by passing a flag to indicate whether the stateobj should be un-
reffed.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40177>
2026-03-03 18:26:08 +00:00
Rob Clark
a95dee6dce freedreno: Avoid shadow blits for compute contexts
A bit ugly, but I think the simplest way to resolve a rusticl specific
race condition.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40177>
2026-03-03 18:26:08 +00:00
Mike Blumenkrantz
653f4c37f4 ntv: run opt_algebraic late for prep optimization pass
must eliminate fcanonicalize

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40151>
2026-03-03 17:59:28 +00:00
Mike Blumenkrantz
be93526ea9 ntv: do gl-style shared/task lowering for vulkan mode
otherwise shaders come in with variables of type shared, which is not
implemented

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40151>
2026-03-03 17:59:28 +00:00
Collabora's Gfx CI Team
dfb4f90a51 Uprev Vulkan Validation Layers
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https://github.com/KhronosGroup/Vulkan-ValidationLayers/compare/snapshot-2026wk07...f020266adee4bb87e8fde219f6fb31f8f141213e

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40032>
2026-03-03 17:24:54 +00:00
Jordan Justen
059dea672e intel/genxml: Update README notes on hardware version numbers
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40103>
2026-03-03 17:03:15 +00:00
Jordan Justen
22796f6cb1 intel/genxml: Start Xe3P (GFX_VERx10 == 350) support (xe3p.xml, xe3p_rt.xml)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40103>
2026-03-03 17:03:15 +00:00
Jordan Justen
475bc596ea intel/genxml: Rename Xe3 genxml to xe3.xml and xe3_rt.xml
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40103>
2026-03-03 17:03:15 +00:00
Jordan Justen
edff8c3ffa intel/genxml: Rename Xe2 genxml to xe2.xml and xe2_rt.xml
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40103>
2026-03-03 17:03:14 +00:00
Jordan Justen
e0f7f44ab8 intel/decoder: Use array of filenames in get_embedded_xml_data_by_name()
The code is a bit simpler to follow. We add new files so rarely, that
it shouldn't be much of a burden add new items.

Reworks:
 * Iván Briano recommended to use array of names rather than more
   complicated filename parsing.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40103>
2026-03-03 17:03:14 +00:00
Karol Herbst
bba6e40ea7 asahi: support subgroup_rotate
This enables cl_khr_subgroup_rotate

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37169>
2026-03-03 16:31:32 +00:00
Karol Herbst
ca30514389 rusticl: support more subgroup extensions
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37169>
2026-03-03 16:31:32 +00:00
Karol Herbst
e167bdf4ac zink: implement subgroup rotate
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37169>
2026-03-03 16:31:32 +00:00
Karol Herbst
db6394babc ac/llvm: handle int8 inside ac_build_optimization_barrier
Rusticl wants to support more subgroup operations and with CL they use
8bit integer sources as well.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37169>
2026-03-03 16:31:31 +00:00
Karol Herbst
dee90bf617 zink: handle drivers with multiple subgroup sizes correctly
This makes use of VK_KHR_pipeline_executable_properties and
VK_EXT_subgroup_size_control to query supported subgroup sizes and to
query which one the driver picks for a given pipeline.

This fixes OpenCL subgroups on drivers with multiple supported subgroup
sizes.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37169>
2026-03-03 16:31:31 +00:00
Lionel Landwerlin
38ef732169 anv: dirty all push constant stages in simple shader
Above we're reprogramming push constants as well at a couple of
workarounds that require dirtying all stages.

cmd_buffer->state.gfx.push_constant_stages was already set in the
above function.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 4fa1eddb4c ("anv: optimize binding table flushing")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14953
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40198>
2026-03-03 16:08:12 +00:00
Pavel Ondračka
85fdbd9bf2 r300/ci: enable HiZ in CI
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This might introduce some flakiness due to the inherent "only one process
can have HyperZ lock" feature. So it might not catch regressions reliably,
but probably better than no coverage at all.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39914>
2026-03-03 15:00:36 +00:00
Pavel Ondračka
b0f019f8cf r300: disable HiZ for PIPE_FUNC_ALWAYS
AMD docs support this:
R5xx Acceleration v1.5 says safest handling for ZFUNC changes is to disable
HiZ except specific LESS/LEQUAL and GREATER/GEQUAL transitions.
ATI OpenGL Programming and Optimization Guide advises avoiding ALWAYS when
trying to benefit from HiZ so that would imply fglrx also disables HiZ
there.

On RV530 this fixes the following dEQPs:
dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.43
dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.74

Fixes: 12dcbd5954 ("r300g: enable Hyper-Z by default on r500")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8093
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39914>
2026-03-03 15:00:36 +00:00
David Rosca
55bab89951 vl: Also disable MPEG2 Main profile when mpeg12 decode is disabled
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Fixes: f4959c16c8 ("meson: add mpeg12dec as a video-codec")
Reviewed-by: Benjamin Cheng <benjamin.cheng@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39672>
2026-03-03 12:15:20 +00:00
Konstantin Seurer
d363381d18 vulkan/cmd_queue: Don't explicitly set struct members to NULL
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They are already initialized by the memcpy above.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39902>
2026-03-03 10:19:31 +00:00
Konstantin Seurer
f2bb6103c3 vulkan/cmd_queue: Rework copy codegen
The new code handles pNext chanis correctly.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39902>
2026-03-03 10:19:31 +00:00
Jose Maria Casanova Crespo
ecb6c5d555 vc4: flush write jobs before BO replacement in DISCARD_WHOLE path
The DISCARD_WHOLE_RESOURCE path in vc4_map_usage_prep() replaces the
resource's BO with vc4_resource_bo_alloc(). As the RCL resolves
rsc->bo at job submit in vc4_submit_setup_rcl_surface(), any pending
write job would store to the new BO instead of the old one, corrupting
the new written data.

This is the same bug that was fixed in v3d in the previous commit.

Fixes: 18ccda7b86 ("vc4: When asked to discard-map a whole resource, discard it.")
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40180>
2026-03-03 09:32:47 +00:00
Jose Maria Casanova Crespo
1eaa46da09 v3d: flush write jobs before BO replacement in DISCARD_WHOLE path
The DISCARD_WHOLE_RESOURCE path in v3d_map_usage_prep() replaces the
resource's BO with v3d_resource_bo_alloc(). As the RCL resolves
rsc->bo at job submit in emit_rcl() any pending write job would
store to the new BO instead of the old one, corrupting the new
written data.

This is adressed by flushing all pending write jobs affecting the
resource before replacing its BO.

This fixes multiple tests where data copied to a renderbuffer was
overwritten by a previos GPU clear. Test are from the subgroup:
dEQP-GLES31.functional.copy_image.non_compressed.viewclass_32_bits.*

Fixes: 45bb8f2957 ("broadcom: Add V3D 3.3 gallium driver called "vc5", for BCM7268.")
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40180>
2026-03-03 09:32:47 +00:00
Rhys Perry
a5f63424c7 ac/gpu_info: print most of ac_compiler_info
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Excluding fields which are copied in ac_gpu_info.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40042>
2026-03-03 08:50:12 +00:00
Rhys Perry
5c3b5688a1 amd: rename ac_cu_info to ac_compiler_info
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40042>
2026-03-03 08:50:12 +00:00
Rhys Perry
ab4b3b7737 ac/nir/ngg: add ac_cu_info shortcut
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40042>
2026-03-03 08:50:12 +00:00
Rhys Perry
a65089dfce ac/nir: pass ac_cu_info to ac_nir_compute_tess_wg_info
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40042>
2026-03-03 08:50:11 +00:00
Rhys Perry
8801ca188d ac/nir: don't pass radeon_info to ac_nir_set_options
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40042>
2026-03-03 08:50:10 +00:00
Rhys Perry
5a8a7dbb22 ac/nir: don't pass radeon_info to NGG lowering
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40042>
2026-03-03 08:50:09 +00:00
Rhys Perry
36feec61c8 ac/nir: use ac_nir_lower_ngg_options for ac_nir_lower_ngg_mesh
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40042>
2026-03-03 08:50:09 +00:00
Rhys Perry
2c7b8e6786 ac/gpu_info: move some NGG flags to ac_cu_info
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40042>
2026-03-03 08:50:09 +00:00
Maaz Mombasawala
2a3c9d5ac6 svga: Use gfx-ci kernel in CI
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We currently use a custom kernel in blu/linux to run the ci for svga,
instead switch to the kernel used by other drivers.

Signed-off-by: Maaz Mombasawala <maaz.mombasawala@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40016>
2026-03-03 00:09:59 +00:00
irql-notlessorequal
74e73b0e21 docs/features: Mark VK_KHR_maintenance6 complete for hasvk
Also does the same for VK_KHR_maintenance5 as that was missed.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37434>
2026-03-02 23:16:11 +00:00
irql-notlessorequal
0988c68eeb hasvk: Advertise VK_KHR_maintenance6
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37434>
2026-03-02 23:16:11 +00:00
irql-notlessorequal
971cca33df hasvk: Add support for Cmd*DescriptorSet*2KHR
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37434>
2026-03-02 23:16:11 +00:00
irql-notlessorequal
9b8cb10e1d hasvk: Handle VkBindMemoryStatusKHR on buffer/image memory bind
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37434>
2026-03-02 23:16:11 +00:00
irql-notlessorequal
da9e9329ec hasvk: Remove no longer valid assert
VK_KHR_maintenance6 allows creating uncompressed views of compressed images with multiple layers.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37434>
2026-03-02 23:16:11 +00:00
irql-notlessorequal
879bbf4e37 hasvk: Allow NULL index buffers
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37434>
2026-03-02 23:16:10 +00:00
Rob Clark
dcbb16a488 ir3: Initialize debug once
Reduce tsan spam.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40178>
2026-03-02 22:47:27 +00:00