Commit graph

1288 commits

Author SHA1 Message Date
Pohjolainen, Topi
042cc201f2 intel/isl: Apply render target alignment constraints for MCS
v2: Instead of having the same block in isl_gen7,8,9.c add it
    once into isl.c::isl_choose_image_alignment_el() instead.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-02-23 12:10:42 -08:00
Lionel Landwerlin
34e29b2ebd intel/isl: add MCS width constraint 16 samples
v3 (Jason Ekstrand): Add a comment explaining why

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
2017-02-23 12:10:42 -08:00
Jason Ekstrand
3885375195 intel/isl: Return surface creation success from aux helpers
The isl_surf_init call that each of these helpers make can, in theory,
fail.  We should propagate that up to the caller rather than just
silently ignoring it.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
2017-02-23 12:10:42 -08:00
Samuel Iglesias Gonsálvez
a9c488f285 isl/state: fix assert on raw buffer surface state minimum size
From IVB PRM, SURFACE_STATE::Height:

"For typed buffer and structured buffer surfaces, the number of
 entries in the buffer ranges from 1 to 2^27 . For raw buffer
 surfaces, the number of entries in the buffer is the number of bytes
 which can range from 1 to 2^30."

The minimum value is 1, according to the spec. The spec quote
was already added into the code by 028f6d8317.

Fixes crashing tests under:

dEQP-VK.robustness.buffer_access.*

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-02-23 11:46:47 +01:00
Jason Ekstrand
1bd0e9ca33 anv/Makefile: Gather all the genX files into one place
While we're here, we also fix the alphabetization of the list of
genx_* files.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-02-22 15:07:18 -08:00
Dylan Baker
8e03250fcf vulkan: Combine wsi and util makefiles
Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-02-22 13:12:02 -08:00
Dylan Baker
e9dcb17962 vulkan/util: Add generator for enum_to_str functions
This adds a python generator to produce enum_to_str functions for
Vulkan from the vk.xml API description. It supports extensions as well
as core API features, and the generator works with both python2 and
python3.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2017-02-22 13:12:02 -08:00
Jason Ekstrand
f31ed6d0cd anv: Take a device parameter in anv_state_flush
This allows the helper to check for llc instead of having to do it
manually at all the call sites.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-02-21 12:26:35 -08:00
Jason Ekstrand
f408971deb anv: Pull all clflushing into a clflush_range helper
All this cache line address calculation stuff is tricky.  Let's not
duplicate it more places than we have to.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-02-21 12:26:35 -08:00
Jason Ekstrand
16b187c8bb anv: Remove the unused state_pool_emit macro
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-02-21 12:26:35 -08:00
Jason Ekstrand
f9d7d27d6d anv: Rename clflush_range and state_clflush
It's a bit shorter and easier to work with.  Also, we're about to add a
helper called clflush which does the clflush but without any memory
fencing.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-02-21 12:26:35 -08:00
Jason Ekstrand
075ed20614 intel/blorp: Explicitly flush all allocated state
Found by inspection.  However, I expect it fixes real bugs when using
blorp from Vulkan on little-core platforms.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
2017-02-21 12:26:35 -08:00
Jason Ekstrand
b6b03329af anv: Put everything about queries in genX_query.c
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-02-21 12:26:35 -08:00
Jason Ekstrand
965fad0e8b anv/Makefile: alphabetize
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-02-21 12:26:35 -08:00
Jason Ekstrand
40087bcb51 anv/query: Perform CmdResetQueryPool on the GPU
This fixes a some rendering corruption in The Talos Principle

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
2017-02-21 12:26:35 -08:00
Jason Ekstrand
dc9abd0e6b genxml: Make MI_STORE_DATA_IMM more consistent
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
2017-02-21 12:26:35 -08:00
Jason Ekstrand
3788cd3239 anv/query: clflush the bo map on non-LLC platforms
Found by inspection

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
2017-02-21 12:26:35 -08:00
Jason Ekstrand
8582ab2d6e anv: Add an invalidate_range helper
This is similar to clflush_range except that it puts the mfence on the
other side to ensure caches are flushed prior to reading.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
2017-02-21 12:26:35 -08:00
Emil Velikov
9807e9dea6 anv: remove unused anv_dispatch_table dtable
Fixes: 4c9dec80ed ("anv: Get rid of the ANV_CALL macro")
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
2017-02-21 18:31:04 +00:00
Emil Velikov
e776e0385c anv: remove unneeded extern C notation
Analogous to previous commit - never used in any C++ code.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2017-02-21 18:28:18 +00:00
Dave Airlie
0a44a680ff vulkan/wsi/x11: add support to detect if we can support rendering (v3)
This adds support to radv_GetPhysicalDeviceXlibPresentationSupportKHR
and radv_GetPhysicalDeviceXcbPresentationSupportKHR to check if the
local device file descriptor is compatible with the descriptor
retrieved from the X server via DRI3.

This will stop radv binding to an X server until we have prime
support in place. Hopefully apps use this API before trying
to render things.

v2: drop unneeded function, don't leak memory. (jekstrand)
v3: also check in surface_get_support callback.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-02-20 12:53:52 +10:00
Jason Ekstrand
5f02c2a054 anv/TODO: Check off Storage Image Without Format
The code for this landed a few days ago.
2017-02-17 14:18:34 -08:00
Matt Turner
656e30b686 anv: Use build-id for pipeline cache UUID.
The --build-id=... ld flag has been present since binutils-2.18,
released 28 Aug 2007.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
2017-02-15 13:59:51 -08:00
Lionel Landwerlin
0fcb92c17d anv: wsi: report presentation error per image request
vkQueuePresentKHR() takes VkPresentInfoKHR pointer and includes a
pResults fields which must holds the results of all the images
requested to be presented. Currently we're not filling this field.

Also as a side effect we probably want to go through all the images
rather than stopping on the first error.

This commit also makes the QueuePresentKHR() implementation return the
first error encountered.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "17.0" <mesa-stable@lists.freedesktop.org>
2017-02-15 11:43:05 +00:00
Jason Ekstrand
bfbb362601 anv: Use vk_foreach_struct for handling extension structs
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-02-14 16:15:39 -08:00
Jason Ekstrand
f434a60a53 anv: Implement the Skylake stencil PMA optimization
Unfortunately, this doesn't substantially improve the performance of any
known apps.  With Dota 2 on my Sky Lake gt4, it seems help by somewhere
between 0% and 1% but there's enough noise that it's hard to get a clear
picture.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2017-02-14 14:18:55 -08:00
Jason Ekstrand
d665c51eea genxml: Add the CACHE_MODE_0 register on gen9
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-02-14 14:18:55 -08:00
Jason Ekstrand
028e1137e6 anv/pipeline: Be smarter about depth/stencil state
It's a bit hard to measure because it almost gets lost in the noise,
but this seemed to help Dota 2 by a percent or two on my Broadwell
GT3e desktop.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2017-02-14 14:18:55 -08:00
Jason Ekstrand
215fed7318 anv/pipeline: Make a copy of VkPipelineDepthStencilStateCreateinfo
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2017-02-14 14:18:55 -08:00
Jason Ekstrand
e8d52dab48 anv: Add support for the PMA fix on Broadwell
This helps Dota 2 on Broadwell by 8-9%.  I also hacked up the driver and
used the Sascha "shadowmapping" demo to get some results.  Setting
uses_kill to true dropped the framerate on the demo by 25-30%.  Enabling
the PMA fix brought it back up to around 90% of the original framerate.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2017-02-14 14:18:55 -08:00
Jason Ekstrand
62bba4ba2d genxml: Add the CACHE_MODE_1 register on gen8
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-02-14 14:18:55 -08:00
Jason Ekstrand
6ce8592836 anv: Disable stencil writes when both write masks are zero
Vulkan doesn't have a stencilWriteEnable bit like it does for depth.
Instead, you have a stencil mask.  Since the stencil mask is handled as
dynamic state, we have to handle it later during command buffer
construction.  This, combined with a later commit, seems to help Dota2
on my Broadwell GT3e desktop by a couple percent because it allows the
hardware to move the depth and stencil writes to early in more cases.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2017-02-14 14:18:55 -08:00
Jason Ekstrand
114c281e70 anv/entrypoints: Only generate entrypoints for supported features
This changes the way anv_entrypoints_gen.py works from generating a
table containing every single entrypoint in the XML to just the ones
that we actually need.  There's no reason for us to burn entrypoint
table space on a bunch of NV extensions we never plan to implement.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-02-14 14:18:55 -08:00
Connor Abbott
6319bfc2a6 anv: fix Get*MemoryRequirements for !LLC
Even though we supported both coherent and non-coherent memory types, we
effectively forced apps to use the coherent types by accident. Found by
inspection, only compile tested.

Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "17.0" <mesa-stable@lists.freedesktop.org>
2017-02-14 13:05:44 -08:00
Alex Smith
924a8cbb40 anv: Add support for shaderStorageImageWriteWithoutFormat
This allows shaders to write to storage images declared with unknown
format if they are decorated with NonReadable ("writeonly" in GLSL).

Previously an image view would always use a lowered format for its
surface state, however when a shader declares a write-only image, we
should use the real format. Since we don't know at view creation time
whether it will be used with only write-only images in shaders, create
two surface states using both the original format and the lowered
format. When emitting the binding table, choose between the states
based on whether the image is declared write-only in the shader.

Tested on both Sascha Willems' computeshader sample (with the original
shaders and ones modified to declare images writeonly and omit their
format qualifiers) and on our own shaders for which we need support
for this.

Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-02-14 08:16:52 -08:00
Jason Ekstrand
2c30918581 anv/apply_pipeline_layout: Set image.write_only to false
This makes our driver robust to changes in spirv_to_nir which would set
this flag on the variable.  Right now, our driver relies on spirv_to_nir
*not* setting var->data.image.write_only for correctness.  Any patch
which implements the shaderStorageImageWriteWithoutFormat will need to
effectively revert this commit.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-02-14 08:16:45 -08:00
Jason Ekstrand
f8dfe9b826 intel/isl: Add format metadata for typed reads/writes
This adds two columns to the format table as well as two helpers for
determining whether or not a given format is supported for typed reads
and writes.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-02-14 07:50:13 -08:00
Jason Ekstrand
0ef14cdc98 anv/cmd_buffer: Return a VkResult from verify_cmd_parser
This fixes a "statement with no effect" compiler warning

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-02-14 07:50:13 -08:00
Jason Ekstrand
d49d275c41 anv/blorp: Don't sanitize the swizzle for blorp_clear
BLORP is now smart enough to handle any swizzle (even those that contain
ZERO or ONE) in a reasonable manner.  Just let BLORP handle it.  This
fixes the following Vulkan CTS tests on Haswell:

 - dEQP-VK.api.image_clearing.clear_color_image.1d_b4g4r4a4_unorm_pack16
 - dEQP-VK.api.image_clearing.clear_color_image.2d_b4g4r4a4_unorm_pack16
 - dEQP-VK.api.image_clearing.clear_color_image.3d_b4g4r4a4_unorm_pack16

Reviewed-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Cc: "17.0" <mesa-stable@lists.freedesktop.org>
2017-02-13 09:24:49 -08:00
Jason Ekstrand
e233db6e93 intel/blorp: Swizzle clear colors on the CPU
It's trivial to swizzle clear colors on the CPU, easily deals with the
hardware restrictions for render target swizzles, and makes swizzled
clears work on all hardware as opposed to just HSW+.

Reviewed-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Cc: "17.0" <mesa-stable@lists.freedesktop.org>
2017-02-13 09:24:43 -08:00
Emil Velikov
a04cb3f8a5 intel/blorp: do not return const data by get_px_size_sa()
Not much point in the const qualifier since we provide a copy to the
user. Resolves the following -Wignored-qualifiers warning.

src/intel/blorp/blorp_blit.c:1857:8: warning: 'const' type qualifier on
return type has no effect [-Wignored-qualifiers]

v2: keep const qualifier of local variable.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-02-10 11:47:12 +00:00
Juan A. Suarez Romero
02264bc6f9 anv/pipeline: set ThreadDispatchEnable conditionally
Set 3DSTATE_WM/ThreadDispatchEnable bit on/off based on the same
conditions as used in the GL version.

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-02-06 10:27:44 +01:00
Nanley Chery
84dbf68378 anv/blorp: Disable resolves for transparent black clears
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-02-03 09:23:13 -08:00
Nanley Chery
93b819154f anv/cmd_buffer: Don't temporarily enable CCS_E within a render pass
Compressing a render target and decompressing it in the same
single-subpass render pass may waste bandwidth. While this may be
beneficial in some circumstances, it does not help in all. Reclaims
about 1.95% FPS for Dota 2 on some configurations.

v2 (Jason Ekstrand):
- Provide a more thorough comment
- Enable CCS_D for input attachments
v3 (Jason Ekstrand):
- Provide performance numbers

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-02-03 09:23:13 -08:00
Jason Ekstrand
37a6f48ceb intel/isl: Add a better comment for format_supports_ccs_e
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2017-02-02 13:33:43 -08:00
Jason Ekstrand
45b3eb4dfc anv: Remove the finishme for CCS_E with storage images
The data port can't handle CCS at all so replace the finishme with
better comments.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2017-02-02 13:33:43 -08:00
Jason Ekstrand
fc9f0db8e3 intel/isl: Assert that we don't use CCS for storage images
I enabled CCS for storage images in the Vulkan driver and ran it through
the CTS.  It didn't result in any hangs but it demonstrated that the data
port cannot handle CCS.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2017-02-02 13:33:43 -08:00
Jason Ekstrand
7e6a9d9c4b intel/isl: Add a formats_are_ccs_e_compatible helper
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2017-02-02 13:33:43 -08:00
Jason Ekstrand
6142e3c07c intel/isl: Add a format_supports_ccs_d helper
Nothing uses this yet but it serves as a nice bit of documentation
that's relatively easy to find.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2017-02-02 13:33:43 -08:00
Jason Ekstrand
ab06fc6684 intel/isl: Rename supports_lossless_compression to supports_ccs_e
The term "lossless compression" could potentially mean multisample
color compression, single-sample color compression or HiZ because they
are all lossless.  The term CCS_E, however, has a very precise meaning;
in ISL and is only used to refer to single-sample color compression.
It's also much shorter which is nice.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2017-02-02 13:33:43 -08:00