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genxml: Add the CACHE_MODE_0 register on gen9

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Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
This commit is contained in:
Jason Ekstrand 2017-02-01 16:39:32 -08:00
parent 028e1137e6
commit d665c51eea
1 changed files with 28 additions and 0 deletions
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28
src/intel/genxml/gen9.xml
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@ -3471,4 +3471,32 @@
<field name="Write Offset" start="2" end="31" type="offset"/>
</register>
<register name="CACHE_MODE_0" length="1" num="0x7000">
<field name="Null tile fix disable" start="0" end="0" type="bool"/>
<field name="Disable clock gating in the pixel backend" start="1" end="1" type="bool"/>
<field name="Hierarchical Z RAW Stall Optimization Disable" start="2" end="2" type="bool"/>
<field name="RCC Eviction Policy" start="4" end="4" type="bool"/>
<field name="STC PMA Optimization Enable" start="5" end="5" type="bool"/>
<field name="Sampler L2 Request Arbitration" start="6" end="7" type="uint">
<value name="Round Robin" value="0"/>
<value name="Fetch are Highest Priority" value="1"/>
<value name="Constants are Highest Priority" value="2"/>
</field>
<field name="Sampler L2 TLB Prefetch Enable" start="9" end="9" type="bool"/>
<field name="Sampler Set Remapping for 3D Disable" start="11" end="11" type="bool"/>
<field name="MSAA Compression Plane Number Threshold for eLLC" start="12" end="14" type="uint"/>
<field name="Sampler L2 Disable" start="15" end="15" type="bool"/>
<field name="Null tile fix disable Mask" start="16" end="16" type="bool"/>
<field name="Disable clock gating in the pixel backend Mask" start="17" end="17" type="bool"/>
<field name="Hierarchical Z RAW Stall Optimization Disable Mask" start="18" end="18" type="bool"/>
<field name="RCC Eviction Policy Mask" start="20" end="20" type="bool"/>
<field name="STC PMA Optimization Enable Mask" start="21" end="21" type="bool"/>
<field name="Sampler L2 Request Arbitration Mask" start="22" end="23" type="uint"/>
<field name="Sampler L2 TLB Prefetch Enable Mask" start="25" end="25" type="bool"/>
<field name="Sampler Set Remapping for 3D Disable Mask" start="27" end="27" type="bool"/>
<field name="MSAA Compression Plane Number Threshold for eLLC Mask" start="28" end="30" type="uint"/>
<field name="Sampler L2 Disable Mask" start="31" end="31" type="bool"/>
</register>
</genxml>