With libetnaviv_parser we are able to parse the resulting string
representation into an etna_inst and assemble that to binary.
As we are not able to parse and/or assemble we need to mark some test
cases with special flags.
This allows us to test: bin -> disasm -> parsing -> assemble
If isa_parse_str(..) is not available we skip this part of the unit
test.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28869>
Implement the following C API's:
- isa_parse_str(..)
- isa_parse_file(..)
- isa_asm_result_destroy(..)
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: @LingMan
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28869>
This commit adds the actual parser, which makes use of the IsaParser
derive proc macro.
It provides two public functions:
- asm_process_str(..)
Parse the provided isa representation and return an etna_asm_result.
This will be used by our unit tests.
- asm_process_file(..)
Parse a whole file full of isa and return an etna_asm_result. This
will be used by our cli assembler.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: @LingMan
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28869>
This struct contains the result of an assembler run and will be filled
in Rust and consumed via a C API.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: @LingMan
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28869>
This proc derive macro does the following magic:
- read static rules file
- parse isaspec xml file
- generate valid pest PEG grammar and attaches it as grammar_inline to
the ast
- calls pest_generator::derive_parser(..) to generate the parser
- creates FromPestRule trait
- creates FromPestRule impl for enums and opcodes
This is the fundation of our assembler.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: @LingMan
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28869>
This commits adds a meta elements with the following attributes:
- has_dest: does the instruction has a dest register?
- valid_srcs: which sources need to be valid?
Is used to generate PEST grammar and defines which of the three source
registers needs to be != void.
- type: which <template> shall be used?
Must match a known template name by the last part.
E.g.: <meta type=tex"/> --> <template name="INSTR_TEX">
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28869>
Will be used for a simple isaspec implementation in rust.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: @LingMan
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28869>
Fixes the following building error:
../out_src/src/intel/common/intel_common.c:29:4: error: implicit declaration of function 'free' is invalid in C99 [-Werror,-Wimplicit-function-declarat
ion]
free(engine_info);
^
1 error generated.
Fixes: 5b8b4f78 ("intel/dev: Add engine_class_supported_count to intel_device_info")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29975>
The CMF values of these formats are not explicitly defined in the
spec. Refer to the added comment for more details.
Fixed Piglit tests:
[ISL_FORMAT_L8A8_UNORM_SRGB]
getteximage-formats -auto -fbo
[ISL_FORMAT_L8_UNORM_SRGB]
teximage-colors GL_SLUMINANCE8 -auto -fbo
[ISL_FORMAT_R9G9B9E5_SHAREDEXP]
fbo-generatemipmap-3d RGB9_E5 -auto -fbo
src/intel/isl/isl_genX_helpers.h:322: isl_get_render_compression_format:
Assertion `!"" "Unsupported render compression format!"' failed.
Also bump up Bspec revision in comments.
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28620>
Current code uses a non-initialized enabled_mask to set the vertex
buffers mask, instead of using the original value from
`so->enabled_mask`
Let's use the original field instead of using an intermediate variable.
Fixes: cbcfb34cf7 ("v3d: use BITSET for the masks")
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29987>
If ring is already current when creating bo, we skip the ring wait but
miss to invalidate bo ring seqno. There's a false-positive for sending a
ring wait upon free memory if the ring has consumed about UINT32_MAX
bytes of traffic (unrelated to ring size).
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29988>
sysmacros.h defines macros `minor()` and `major()`. These macros conflict
with a definition of `minor()` in the Perfetto SDK header. Move the
sysmacros.h include to intel_perf.c because the Perfetto header is only
included at the same time as intel_perf.h not *.c (in intel_driver_ds.cc).
Unbeknown to anyone, the definition of `minor()` in the Perfetto header is
being replaced with the macro. See the MR attachment for an example.
Signed-off-by: Renato Pereyra <renatopereyra@chromium.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29974>
Newer hardware is smart enough to know that if something writes to a
NULL tile and immediately reads back the value (from the cache), the
value should read back as zero, not whatever was written to the cache
but not the memory. Due to that, we don't need to flush the tile
cache, which is quite expensive.
Link: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11029
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29953>
Indirect addressing(vx1 and vxh) not supported with UB/B datatype for
src0, so we need to change the data type for both dest and src0.
This fixes following tests cases on Xe2+
- dEQP-VK.spirv_assembly.instruction.compute.8bit_storage.push_constant_8_to_16*
- dEQP-VK.spirv_assembly.instruction.compute.8bit_storage.push_constant_8_to_32*
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29316>
We can do CSEL on F, HF, *W, and *D on Gfx11+. Gfx9 can only do F.
We can lower unsupported types to CMP+CSEL, allowing us to use CSEL
in the IR and not worry about the limitations.
Rework: (Sagar)
- Update validation pass for CSEL
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29316>
Coverity has spotted a place where we could in theory overflow. In
reality it wont happen as the potential overflow is a bitfield with a
maximum of two values. Add an `assume()` statement to help out the
compiler and document our assumption.
fixes: dc1aedef2b
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29825>
