We are not supposed to apply the vertex index offset to our varying or
non-VS attribute (AKA image) descriptors. While at it, explicitly set
offset_enable to true when emitting vertex attribute descriptors, to
clarify our intentions.
Fixes: c0d6539827 ("panvk: Drop support for Midgard")
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28182>
In NAK, halt turns int OpExit so this gives us exactly the same behavior
as before, just with the increased ability of NIR and our controlf-flow
lowering pass to reason about it.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28300>
This pass lowers from NIR structured control-flow to unstructured
control-flow with sync instructions scattered throughout to ensure
uniform convergence. Unlike the previous nak_nir_add_barriers() pass,
this one actually handles loop continues correctly. The previous pass
had no plan for handling divergent early continues whereas this pass
should. Also, the previous pass attempted to use barrier breaks in a
way that don't actually work because not all lanes involved in the
barrier were involved in the break.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28300>
This is just a little handle to tell the back-end where to do the copy.
Ideally, we'd have a NIR intrinsic that does the copy but we need to be
able to copy any number of registers up to 34 and NIR intrinsics just
aren't that flexible.
Reviewed-by: M Henning <drawoc@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28300>
This way we avoid destroying divergence information which may be used by
passes which also need to lower phis.
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28300>
This fixes nir_print for unstructured control-flow. It's safe to
backport just this patch because the worst case is that we don't set as
many types and not as much gets printed.
Fixes: 260a9167db ("nir/print: Improve NIR_PRINT=print_consts by using nir_gather_ssa_types()")
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28300>
For any reg we can lower, we remove it whenever we remove the last read
or write. For regs that aren't used at all, however, there are no reads
or writes so there's nothing to trigger the removal. Instead, we need
to do it in setup_reg.
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28300>
These are both handled by inserting them directly at the top of the
nir_function_impl. However, if the cursor is already at the top, it
never gets updated so we end up inserting other stuff after the newly
inserted undef or decl_reg. It's an odd edge case to be sure but I hit
it with my new NIR CF pass for NAK.
Fixes: 1be4c61c95 ("nir/builder: Add a helper for creating undefs")
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28300>
Mark arb_tessellation_shader-tes-gs-max-output as flake because
it passes with ESO but crashes with pipelines (existing failure).
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28295>
It is only taking effect in hevc encoding so far.
Cc: mesa-stable
Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28280>
set [64x16] as the alignment for hevc
encoding surface.
Cc: mesa-stable
Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28280>
A750 adds explicit definition of PC_TESS_PARAM_SIZE and
PC_TESS_FACTOR_SIZE, probably in order to to correctly overlap execution
of several draws.
Note that blob adds a bit more space ({0x10, 0x20, 0x30, 0x40} bytes)
to PC_TESS_FACTOR_SIZE than we are, but the purpose of this additional
space is unknown.
Emitting these regs on whole A7XX seem to be fine - A740 doesn't
complain.
Fixes GPU faults in Witcher 3.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28210>
NGG culling depends on the number of FS input reads but this can be
unknown with GPL/ESO when VS/TES are compiled separately. While VS
has a prolog most of the time, TES might incorrectly enable NGG culling
because the number of FS inputs was considered to be zero. To fix that,
consider the number of FS input reads to be the maximum possible value
when the FS is unknown to implicitly disable NGG culling.
This fixes a bunch of tess related flakes with Zink/ESO/RADV on RDNA2.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28293>
We will use struct etna_inst as starting point for our new assembler. The goal is
to do a smooth translation for the gallium driver.
Also apply clang-format rules and use SPDX license tag.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28183>
