radeonsi/vcn: add enc surface alignment caps

set [64x16] as the alignment for hevc
encoding surface.

Cc: mesa-stable
Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28280>

src/amd/common/ac_surface.h

@@ -76,6 +76,12 @@ enum radeon_micro_mode
 #define RADEON_SURF_NO_TEXTURE            (1ull << 34)
 #define RADEON_SURF_NO_STENCIL_ADJUST     (1ull << 35)
 
+enum radeon_enc_hevc_surface_alignment
+{
+   RADEON_ENC_HEVC_SURFACE_LOG2_WIDTH_ALIGNMENT = 6,
+   RADEON_ENC_HEVC_SURFACE_LOG2_HEIGHT_ALIGNMENT = 4,
+};
+
 struct legacy_surf_level {
    uint32_t offset_256B;   /* divided by 256, the hw can only do 40-bit addresses */
    uint32_t slice_size_dw; /* in dwords; max = 4GB / 4. */

src/gallium/drivers/radeonsi/si_get.c

@@ -837,6 +837,18 @@ static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profil
          }
          else
             return 0;
+      case PIPE_VIDEO_CAP_ENC_SURFACE_ALIGNMENT:
+           if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
+               profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10) {
+            union pipe_enc_cap_surface_alignment attrib;
+            attrib.value = 0;
+
+            attrib.bits.log2_width_alignment = RADEON_ENC_HEVC_SURFACE_LOG2_WIDTH_ALIGNMENT;
+            attrib.bits.log2_height_alignment = RADEON_ENC_HEVC_SURFACE_LOG2_HEIGHT_ALIGNMENT;
+            return attrib.value;
+         }
+         else
+            return 0;
 
       default:
          return 0;

src/gallium/include/pipe/p_video_enums.h

@@ -161,6 +161,10 @@ enum pipe_video_cap
     * Encoding Region Of Interest feature
     */
    PIPE_VIDEO_CAP_ENC_ROI = 49,
+   /*
+    * Encoding surface width/height alignment
+    */
+   PIPE_VIDEO_CAP_ENC_SURFACE_ALIGNMENT = 50,
 };
 
 enum pipe_video_h264_enc_dbk_filter_mode_flags

src/gallium/include/pipe/p_video_state.h

@@ -2015,6 +2015,21 @@ union pipe_enc_cap_roi {
    uint32_t value;
 };
 
+union pipe_enc_cap_surface_alignment {
+   struct {
+      /**
+       * log2_width_alignment
+       */
+      uint32_t log2_width_alignment                 : 4;
+      /**
+       * log2_height_alignment
+       */
+      uint32_t log2_height_alignment                : 4;
+      uint32_t reserved                             : 24;
+   } bits;
+   uint32_t value;
+};
+
 #ifdef __cplusplus
 }
 #endif