From f88d6cf79553559452b1f8e161d5b076526c13e2 Mon Sep 17 00:00:00 2001 From: Caio Oliveira Date: Tue, 2 Sep 2025 11:28:43 -0700 Subject: [PATCH] brw: Run validation as soon as we have the CFG around Fixes: affa7567c29 ("intel/brw: Add phases to backend") Reviewed-by: Lionel Landwerlin Part-of: (cherry picked from commit 4e253184de021f12b077461723dcbe2ff389af4e) --- .pick_status.json | 2 +- src/intel/compiler/brw_validate.cpp | 7 +++---- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/.pick_status.json b/.pick_status.json index 50a990f56e3..98d2e94374f 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -9864,7 +9864,7 @@ "description": "brw: Run validation as soon as we have the CFG around", "nominated": true, "nomination_type": 2, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": "affa7567c291b9125afbd062ab77ed82d33330b6", "notes": null diff --git a/src/intel/compiler/brw_validate.cpp b/src/intel/compiler/brw_validate.cpp index 20d48648b1d..15b530185c8 100644 --- a/src/intel/compiler/brw_validate.cpp +++ b/src/intel/compiler/brw_validate.cpp @@ -291,12 +291,11 @@ brw_validate(const brw_shader &s) { const intel_device_info *devinfo = s.devinfo; - if (s.cfg) - s.cfg->validate(_mesa_shader_stage_to_abbrev(s.stage)); - - if (s.phase <= BRW_SHADER_PHASE_AFTER_NIR) + if (!s.cfg) return; + s.cfg->validate(_mesa_shader_stage_to_abbrev(s.stage)); + foreach_block(block, s.cfg) { /* Track the last used address register. Usage of the address register * in the IR should be limited to within a block, otherwise we would