From e65e62b17f40c96bc2fe06ed23c8886164bb67cc Mon Sep 17 00:00:00 2001 From: Sagar Ghuge Date: Wed, 22 Apr 2026 22:16:20 -0700 Subject: [PATCH] intel/genxml: Disable compute walker mid-thread preemption MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On Xe, we have this bit reversed. It's called Thread preemption Disable. On Xe2+ (Bspec 56590), it's called Thread preemption with option enabled/disabled. AFAIK, we don't support mid-thread preemption. This patch set values properly according to bspec. Signed-off-by: Sagar Ghuge Reviewed-by: Tapani Pälli Part-of: --- src/intel/genxml/xe2.xml | 2 +- src/intel/genxml/xe3.xml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/intel/genxml/xe2.xml b/src/intel/genxml/xe2.xml index 8b12e296671..a0984f6c450 100644 --- a/src/intel/genxml/xe2.xml +++ b/src/intel/genxml/xe2.xml @@ -64,7 +64,7 @@ - + diff --git a/src/intel/genxml/xe3.xml b/src/intel/genxml/xe3.xml index f747831eee9..1569065bdb4 100644 --- a/src/intel/genxml/xe3.xml +++ b/src/intel/genxml/xe3.xml @@ -53,7 +53,7 @@ - +