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radeonsi: add gfx11.7

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Reviewed-by: Marek Olšák <maraeo@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40866>
This commit is contained in:
Ganesh Belgur Ramachandra 2026-03-23 22:24:04 +00:00
parent 5ea995893b
commit dc2016892e
11 changed files with 30 additions and 10 deletions
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1
src/gallium/drivers/radeonsi/ci/radeonsi-run-tests.py
View file

@ -324,6 +324,7 @@ def gfx_level_to_str(cl):
"gfx10_3",
"gfx11",
"gfx11_5",
"gfx11_7",
"gfx12",
]
if 8 <= cl and cl < 8 + len(supported):

2
src/gallium/drivers/radeonsi/meson.build
View file

@ -139,7 +139,7 @@ if with_gfx_compute
'si_test_image_copy_region.c',
)
foreach ver : ['6', '7', '8', '9', '10', '103', '11', '115', '12']
foreach ver : ['6', '7', '8', '9', '10', '103', '11', '115', '117', '12']
radeonsi_gfx_libs += static_library(
'radeonsi_gfx@0@'.format(ver),
['si_state_draw.cpp'],

2
src/gallium/drivers/radeonsi/si_clear.c
View file

@ -1053,7 +1053,7 @@ static void gfx6_clear(struct pipe_context *ctx, unsigned buffers,
/* TODO: This hack fixes dEQP-GLES[23].functional.fragment_ops.random.* on Navi31.
* The root cause is unknown.
*/
if (sctx->gfx_level == GFX11 || sctx->gfx_level == GFX11_5)
if (sctx->gfx_level >= GFX11 && sctx->gfx_level < GFX12)
si_set_barrier_flags(sctx, SI_BARRIER_SYNC_VS);
}

4
src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c
View file

@ -15,12 +15,12 @@ bool si_init_cp_reg_shadowing(struct si_context *sctx)
return false;
if (sctx->uses_userq_reg_shadowing) {
/* In case of GFX11_5, shadow_va passed in ac_drm_create_userqueue() is not used by the
/* In case of GFX11.5-11.7, shadow_va passed in ac_drm_create_userqueue() is not used by the
* firmware. Instead need to initialize the register shadowing addresses using LOAD_* packets.
* Also the LOAD_* packets and enabling register shadowing in CONTEXT_CONTROL packet has to
* be submitted for every job.
*/
if (sctx->gfx_level == GFX11_5) {
if (sctx->gfx_level == GFX11_5 || sctx->gfx_level == GFX11_7) {
struct ac_pm4_state *shadowing_pm4 = ac_pm4_create_sized(&sctx->screen->info, false, 1024,
sctx->is_gfx_queue);
if (!shadowing_pm4) {

2
src/gallium/drivers/radeonsi/si_gfx_cs.c
View file

@ -158,7 +158,7 @@ void si_flush_gfx_cs(struct si_context *ctx, unsigned flags, struct pipe_fence_h
/* If we use s_sendmsg to set tess factors to all 0 or all 1 instead of writing to the tess
* factor buffer, we need this at the end of command buffers:
*/
if ((ctx->gfx_level == GFX11 || ctx->gfx_level == GFX11_5) && ctx->has_tessellation) {
if ((ctx->gfx_level >= GFX11 && ctx->gfx_level < GFX12) && ctx->has_tessellation) {
radeon_begin(cs);
radeon_event_write(V_028A90_SQ_NON_EVENT);
radeon_end();

3
src/gallium/drivers/radeonsi/si_pipe.c
View file

@ -750,6 +750,9 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, unsign
case GFX11_5:
si_init_draw_functions_GFX11_5(sctx);
break;
case GFX11_7:
si_init_draw_functions_GFX11_7(sctx);
break;
case GFX12:
si_init_draw_functions_GFX12(sctx);
break;

1
src/gallium/drivers/radeonsi/si_sdma_copy_image.c
View file

@ -434,6 +434,7 @@ bool si_sdma_copy_image(struct si_context *sctx, struct si_texture *dst, struct
case GFX10_3:
case GFX11:
case GFX11_5:
case GFX11_7:
case GFX12:
if (!si_sdma_v4_v5_copy_texture(sctx, dst, src))
return false;

8
src/gallium/drivers/radeonsi/si_state.c
View file

@ -1832,7 +1832,7 @@ static void si_emit_db_render_state(struct si_context *sctx, unsigned index)
S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4) |
S_028010_CENTROID_COMPUTATION_MODE(sctx->gfx_level >= GFX10_3 ? 1 : 0);
if (sctx->gfx_level <= GFX11_5) {
if (sctx->gfx_level <= GFX11_7) {
db_render_override2 |=
S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear);
@ -2408,7 +2408,7 @@ static void si_init_depth_surface(struct si_context *sctx)
.num_samples = tex->buffer.b.b.nr_samples,
.first_layer = sctx->framebuffer.state.zsbuf.first_layer,
.last_layer = sctx->framebuffer.state.zsbuf.last_layer,
.allow_expclear = sctx->gfx_level <= GFX11_5,
.allow_expclear = sctx->gfx_level <= GFX11_7,
.htile_enabled = sctx->gfx_level < GFX12 && si_htile_enabled(tex, level, PIPE_MASK_ZS),
.htile_stencil_disabled = tex->htile_stencil_disabled,
};
@ -4952,10 +4952,10 @@ static bool gfx10_init_gfx_preamble_state(struct si_context *sctx)
}
if (sctx->uses_userq_reg_shadowing) {
/* In case of GFX11_5, CONTEXT_CONTROL packet is added in si_init_cp_reg_shaodwing()
/* In case of GFX11.5-11.7, CONTEXT_CONTROL packet is added in si_init_cp_reg_shaodwing()
* function.
*/
if (sctx->gfx_level != GFX11_5) {
if (sctx->gfx_level < GFX11_5 || sctx->gfx_level > GFX11_7) {
ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
ac_pm4_cmd_add(&pm4->base, S_281_UPDATE_LOAD_ENABLES(1) | S_281_LOAD_PER_CONTEXT_STATE(1) |
S_281_LOAD_CS_SH_REGS(1) | S_281_LOAD_GFX_SH_REGS(1) |

1
src/gallium/drivers/radeonsi/si_state.h
View file

@ -534,6 +534,7 @@ void si_init_draw_functions_GFX10(struct si_context *sctx);
void si_init_draw_functions_GFX10_3(struct si_context *sctx);
void si_init_draw_functions_GFX11(struct si_context *sctx);
void si_init_draw_functions_GFX11_5(struct si_context *sctx);
void si_init_draw_functions_GFX11_7(struct si_context *sctx);
void si_init_draw_functions_GFX12(struct si_context *sctx);
/* si_state_msaa.c */

15
src/gallium/drivers/radeonsi/si_state_draw.cpp
View file

@ -33,6 +33,8 @@
#define GFX(name) name##GFX11
#elif (GFX_VER == 115)
#define GFX(name) name##GFX11_5
#elif (GFX_VER == 117)
#define GFX(name) name##GFX11_7
#elif (GFX_VER == 12)
#define GFX(name) name##GFX12
#else
@ -432,6 +434,8 @@ bool si_update_shaders_for_mesh(struct si_context *sctx, struct si_shader *old_v
return si_update_shaders_shared_by_vertex_and_mesh_pipe<GFX11, TESS_OFF, GS_OFF, MS_ON, NGG_ON>(sctx, old_vs, new_vs);
case GFX11_5:
return si_update_shaders_shared_by_vertex_and_mesh_pipe<GFX11_5, TESS_OFF, GS_OFF, MS_ON, NGG_ON>(sctx, old_vs, new_vs);
case GFX11_7:
return si_update_shaders_shared_by_vertex_and_mesh_pipe<GFX11_7, TESS_OFF, GS_OFF, MS_ON, NGG_ON>(sctx, old_vs, new_vs);
case GFX12:
return si_update_shaders_shared_by_vertex_and_mesh_pipe<GFX12, TESS_OFF, GS_OFF, MS_ON, NGG_ON>(sctx, old_vs, new_vs);
default:
@ -698,6 +702,9 @@ void si_cp_dma_prefetch(struct radeon_cmdbuf *cs,
case GFX11_5:
si_cp_dma_prefetch_inline<GFX11_5>(cs, address, size);
break;
case GFX11_7:
si_cp_dma_prefetch_inline<GFX11_7>(cs, address, size);
break;
case GFX12:
si_cp_dma_prefetch_inline<GFX12>(cs, address, size);
break;
@ -1098,6 +1105,9 @@ void si_emit_rasterizer_prim_state_for_mesh(struct si_context *sctx)
case GFX11_5:
si_emit_rasterizer_prim_state<GFX11_5, GS_OFF, NGG_ON>(sctx);
break;
case GFX11_7:
si_emit_rasterizer_prim_state<GFX11_7, GS_OFF, NGG_ON>(sctx);
break;
case GFX12:
si_emit_rasterizer_prim_state<GFX12, GS_OFF, NGG_ON>(sctx);
break;
@ -1816,7 +1826,7 @@ static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw
}
}
} else {
if ((GFX_VERSION == GFX11_5 || GFX_VERSION == GFX12) && !IS_DRAW_VERTEX_STATE &&
if ((GFX_VERSION >= GFX11_5 && GFX_VERSION <= GFX12) && !IS_DRAW_VERTEX_STATE &&
indirect && indirect->count_from_stream_output) {
/* DrawTransformFeedback requires 3 SQ_NON_EVENTs after the packet. */
assert(num_draws == 1);
@ -1933,6 +1943,9 @@ void si_set_vertex_buffer_descriptor(struct si_screen *sscreen, struct si_vertex
case GFX11_5:
si_set_vb_descriptor<GFX11_5>(velems, vb, element_index, out);
break;
case GFX11_7:
si_set_vb_descriptor<GFX11_7>(velems, vb, element_index, out);
break;
case GFX12:
si_set_vb_descriptor<GFX12>(velems, vb, element_index, out);
break;

1
src/gallium/drivers/radeonsi/si_texture.c
View file

@ -365,6 +365,7 @@ static int si_init_surface(struct si_screen *sscreen, struct radeon_surf *surfac
case GFX11:
case GFX11_5:
case GFX11_7:
break;
default: