From dc2016892ed0f3112b4acbe6e37682ab16a75a41 Mon Sep 17 00:00:00 2001 From: Ganesh Belgur Ramachandra Date: Mon, 23 Mar 2026 22:24:04 +0000 Subject: [PATCH] radeonsi: add gfx11.7 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Marek Olšák Part-of: --- .../drivers/radeonsi/ci/radeonsi-run-tests.py | 1 + src/gallium/drivers/radeonsi/meson.build | 2 +- src/gallium/drivers/radeonsi/si_clear.c | 2 +- .../drivers/radeonsi/si_cp_reg_shadowing.c | 4 ++-- src/gallium/drivers/radeonsi/si_gfx_cs.c | 2 +- src/gallium/drivers/radeonsi/si_pipe.c | 3 +++ src/gallium/drivers/radeonsi/si_sdma_copy_image.c | 1 + src/gallium/drivers/radeonsi/si_state.c | 8 ++++---- src/gallium/drivers/radeonsi/si_state.h | 1 + src/gallium/drivers/radeonsi/si_state_draw.cpp | 15 ++++++++++++++- src/gallium/drivers/radeonsi/si_texture.c | 1 + 11 files changed, 30 insertions(+), 10 deletions(-) diff --git a/src/gallium/drivers/radeonsi/ci/radeonsi-run-tests.py b/src/gallium/drivers/radeonsi/ci/radeonsi-run-tests.py index 9e88e66ed77..19a47fc1ab4 100755 --- a/src/gallium/drivers/radeonsi/ci/radeonsi-run-tests.py +++ b/src/gallium/drivers/radeonsi/ci/radeonsi-run-tests.py @@ -324,6 +324,7 @@ def gfx_level_to_str(cl): "gfx10_3", "gfx11", "gfx11_5", + "gfx11_7", "gfx12", ] if 8 <= cl and cl < 8 + len(supported): diff --git a/src/gallium/drivers/radeonsi/meson.build b/src/gallium/drivers/radeonsi/meson.build index 02aba1d31a9..9c4b583f0a9 100644 --- a/src/gallium/drivers/radeonsi/meson.build +++ b/src/gallium/drivers/radeonsi/meson.build @@ -139,7 +139,7 @@ if with_gfx_compute 'si_test_image_copy_region.c', ) - foreach ver : ['6', '7', '8', '9', '10', '103', '11', '115', '12'] + foreach ver : ['6', '7', '8', '9', '10', '103', '11', '115', '117', '12'] radeonsi_gfx_libs += static_library( 'radeonsi_gfx@0@'.format(ver), ['si_state_draw.cpp'], diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c index dfc470bd26a..3bd5abeec8f 100644 --- a/src/gallium/drivers/radeonsi/si_clear.c +++ b/src/gallium/drivers/radeonsi/si_clear.c @@ -1053,7 +1053,7 @@ static void gfx6_clear(struct pipe_context *ctx, unsigned buffers, /* TODO: This hack fixes dEQP-GLES[23].functional.fragment_ops.random.* on Navi31. * The root cause is unknown. */ - if (sctx->gfx_level == GFX11 || sctx->gfx_level == GFX11_5) + if (sctx->gfx_level >= GFX11 && sctx->gfx_level < GFX12) si_set_barrier_flags(sctx, SI_BARRIER_SYNC_VS); } diff --git a/src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c b/src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c index 217b114473a..b62b8803100 100644 --- a/src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c +++ b/src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c @@ -15,12 +15,12 @@ bool si_init_cp_reg_shadowing(struct si_context *sctx) return false; if (sctx->uses_userq_reg_shadowing) { - /* In case of GFX11_5, shadow_va passed in ac_drm_create_userqueue() is not used by the + /* In case of GFX11.5-11.7, shadow_va passed in ac_drm_create_userqueue() is not used by the * firmware. Instead need to initialize the register shadowing addresses using LOAD_* packets. * Also the LOAD_* packets and enabling register shadowing in CONTEXT_CONTROL packet has to * be submitted for every job. */ - if (sctx->gfx_level == GFX11_5) { + if (sctx->gfx_level == GFX11_5 || sctx->gfx_level == GFX11_7) { struct ac_pm4_state *shadowing_pm4 = ac_pm4_create_sized(&sctx->screen->info, false, 1024, sctx->is_gfx_queue); if (!shadowing_pm4) { diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c index 9b76d89684a..baa22967e3f 100644 --- a/src/gallium/drivers/radeonsi/si_gfx_cs.c +++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c @@ -158,7 +158,7 @@ void si_flush_gfx_cs(struct si_context *ctx, unsigned flags, struct pipe_fence_h /* If we use s_sendmsg to set tess factors to all 0 or all 1 instead of writing to the tess * factor buffer, we need this at the end of command buffers: */ - if ((ctx->gfx_level == GFX11 || ctx->gfx_level == GFX11_5) && ctx->has_tessellation) { + if ((ctx->gfx_level >= GFX11 && ctx->gfx_level < GFX12) && ctx->has_tessellation) { radeon_begin(cs); radeon_event_write(V_028A90_SQ_NON_EVENT); radeon_end(); diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index e2b07b6ca34..da9918ef4cf 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -750,6 +750,9 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, unsign case GFX11_5: si_init_draw_functions_GFX11_5(sctx); break; + case GFX11_7: + si_init_draw_functions_GFX11_7(sctx); + break; case GFX12: si_init_draw_functions_GFX12(sctx); break; diff --git a/src/gallium/drivers/radeonsi/si_sdma_copy_image.c b/src/gallium/drivers/radeonsi/si_sdma_copy_image.c index f44ee38b4e6..697f285208f 100644 --- a/src/gallium/drivers/radeonsi/si_sdma_copy_image.c +++ b/src/gallium/drivers/radeonsi/si_sdma_copy_image.c @@ -434,6 +434,7 @@ bool si_sdma_copy_image(struct si_context *sctx, struct si_texture *dst, struct case GFX10_3: case GFX11: case GFX11_5: + case GFX11_7: case GFX12: if (!si_sdma_v4_v5_copy_texture(sctx, dst, src)) return false; diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index d44a61e2643..a8bda2a21f4 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -1832,7 +1832,7 @@ static void si_emit_db_render_state(struct si_context *sctx, unsigned index) S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4) | S_028010_CENTROID_COMPUTATION_MODE(sctx->gfx_level >= GFX10_3 ? 1 : 0); - if (sctx->gfx_level <= GFX11_5) { + if (sctx->gfx_level <= GFX11_7) { db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) | S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear); @@ -2408,7 +2408,7 @@ static void si_init_depth_surface(struct si_context *sctx) .num_samples = tex->buffer.b.b.nr_samples, .first_layer = sctx->framebuffer.state.zsbuf.first_layer, .last_layer = sctx->framebuffer.state.zsbuf.last_layer, - .allow_expclear = sctx->gfx_level <= GFX11_5, + .allow_expclear = sctx->gfx_level <= GFX11_7, .htile_enabled = sctx->gfx_level < GFX12 && si_htile_enabled(tex, level, PIPE_MASK_ZS), .htile_stencil_disabled = tex->htile_stencil_disabled, }; @@ -4952,10 +4952,10 @@ static bool gfx10_init_gfx_preamble_state(struct si_context *sctx) } if (sctx->uses_userq_reg_shadowing) { - /* In case of GFX11_5, CONTEXT_CONTROL packet is added in si_init_cp_reg_shaodwing() + /* In case of GFX11.5-11.7, CONTEXT_CONTROL packet is added in si_init_cp_reg_shaodwing() * function. */ - if (sctx->gfx_level != GFX11_5) { + if (sctx->gfx_level < GFX11_5 || sctx->gfx_level > GFX11_7) { ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); ac_pm4_cmd_add(&pm4->base, S_281_UPDATE_LOAD_ENABLES(1) | S_281_LOAD_PER_CONTEXT_STATE(1) | S_281_LOAD_CS_SH_REGS(1) | S_281_LOAD_GFX_SH_REGS(1) | diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h index ef4c0ce88f5..e0fc6786657 100644 --- a/src/gallium/drivers/radeonsi/si_state.h +++ b/src/gallium/drivers/radeonsi/si_state.h @@ -534,6 +534,7 @@ void si_init_draw_functions_GFX10(struct si_context *sctx); void si_init_draw_functions_GFX10_3(struct si_context *sctx); void si_init_draw_functions_GFX11(struct si_context *sctx); void si_init_draw_functions_GFX11_5(struct si_context *sctx); +void si_init_draw_functions_GFX11_7(struct si_context *sctx); void si_init_draw_functions_GFX12(struct si_context *sctx); /* si_state_msaa.c */ diff --git a/src/gallium/drivers/radeonsi/si_state_draw.cpp b/src/gallium/drivers/radeonsi/si_state_draw.cpp index 8b9de9431d5..52d2b47af9a 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.cpp +++ b/src/gallium/drivers/radeonsi/si_state_draw.cpp @@ -33,6 +33,8 @@ #define GFX(name) name##GFX11 #elif (GFX_VER == 115) #define GFX(name) name##GFX11_5 +#elif (GFX_VER == 117) +#define GFX(name) name##GFX11_7 #elif (GFX_VER == 12) #define GFX(name) name##GFX12 #else @@ -432,6 +434,8 @@ bool si_update_shaders_for_mesh(struct si_context *sctx, struct si_shader *old_v return si_update_shaders_shared_by_vertex_and_mesh_pipe(sctx, old_vs, new_vs); case GFX11_5: return si_update_shaders_shared_by_vertex_and_mesh_pipe(sctx, old_vs, new_vs); + case GFX11_7: + return si_update_shaders_shared_by_vertex_and_mesh_pipe(sctx, old_vs, new_vs); case GFX12: return si_update_shaders_shared_by_vertex_and_mesh_pipe(sctx, old_vs, new_vs); default: @@ -698,6 +702,9 @@ void si_cp_dma_prefetch(struct radeon_cmdbuf *cs, case GFX11_5: si_cp_dma_prefetch_inline(cs, address, size); break; + case GFX11_7: + si_cp_dma_prefetch_inline(cs, address, size); + break; case GFX12: si_cp_dma_prefetch_inline(cs, address, size); break; @@ -1098,6 +1105,9 @@ void si_emit_rasterizer_prim_state_for_mesh(struct si_context *sctx) case GFX11_5: si_emit_rasterizer_prim_state(sctx); break; + case GFX11_7: + si_emit_rasterizer_prim_state(sctx); + break; case GFX12: si_emit_rasterizer_prim_state(sctx); break; @@ -1816,7 +1826,7 @@ static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw } } } else { - if ((GFX_VERSION == GFX11_5 || GFX_VERSION == GFX12) && !IS_DRAW_VERTEX_STATE && + if ((GFX_VERSION >= GFX11_5 && GFX_VERSION <= GFX12) && !IS_DRAW_VERTEX_STATE && indirect && indirect->count_from_stream_output) { /* DrawTransformFeedback requires 3 SQ_NON_EVENTs after the packet. */ assert(num_draws == 1); @@ -1933,6 +1943,9 @@ void si_set_vertex_buffer_descriptor(struct si_screen *sscreen, struct si_vertex case GFX11_5: si_set_vb_descriptor(velems, vb, element_index, out); break; + case GFX11_7: + si_set_vb_descriptor(velems, vb, element_index, out); + break; case GFX12: si_set_vb_descriptor(velems, vb, element_index, out); break; diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c index da4762d1950..52007579515 100644 --- a/src/gallium/drivers/radeonsi/si_texture.c +++ b/src/gallium/drivers/radeonsi/si_texture.c @@ -365,6 +365,7 @@ static int si_init_surface(struct si_screen *sscreen, struct radeon_surf *surfac case GFX11: case GFX11_5: + case GFX11_7: break; default: