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amd: add initial common code for gfx11.7

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Reviewed-by: Marek Olšák <maraeo@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40866>
This commit is contained in:
Ganesh Belgur Ramachandra 2026-03-23 22:21:02 +00:00
parent fcfdd4cfea
commit 5ea995893b
10 changed files with 38 additions and 13 deletions
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2
src/amd/common/ac_descriptors.c
View file

@ -1124,7 +1124,7 @@ ac_set_mutable_ds_surface_fields(const struct radeon_info *info, const struct ac
log_num_samples = G_028040_NUM_SAMPLES(ds->db_z_info);
}
bool z_allow_expclear = info->gfx_level <= GFX11_5 &&
bool z_allow_expclear = info->gfx_level <= GFX11_7 &&
G_028038_ALLOW_EXPCLEAR(ds->db_z_info);
const uint32_t max_zplanes =

7
src/amd/common/ac_gpu_info.c
View file

@ -394,7 +394,7 @@ ac_fill_compiler_info(struct radeon_info *info, const struct drm_amdgpu_info_dev
* attributes may be corrupted.
* The workaround is to issue and wait for attribute stores before the last export.
*/
out->has_attr_ring_wait_bug = info->gfx_level == GFX11 || info->gfx_level == GFX11_5;
out->has_attr_ring_wait_bug = info->gfx_level >= GFX11 && info->gfx_level < GFX12;
out->has_primid_instancing_bug = info->gfx_level == GFX6 && info->max_se == 1;
}
@ -694,6 +694,9 @@ ac_identify_chip(struct radeon_info *info, const struct drm_amdgpu_info_device *
identify_chip(KRACKAN1);
identify_chip(GFX1153);
break;
case FAMILY_GFX1170:
identify_chip(GFX1170);
break;
case FAMILY_NV4:
identify_chip(GFX1200);
identify_chip(GFX1201);
@ -708,6 +711,8 @@ ac_identify_chip(struct radeon_info *info, const struct drm_amdgpu_info_device *
if (info->ip[AMD_IP_GFX].ver_major == 12 && info->ip[AMD_IP_GFX].ver_minor == 0)
info->gfx_level = GFX12;
else if (info->ip[AMD_IP_GFX].ver_major == 11 && info->ip[AMD_IP_GFX].ver_minor == 7)
info->gfx_level = GFX11_7;
else if (info->ip[AMD_IP_GFX].ver_major == 11 && info->ip[AMD_IP_GFX].ver_minor == 5)
info->gfx_level = GFX11_5;
else if (info->ip[AMD_IP_GFX].ver_major == 11 && info->ip[AMD_IP_GFX].ver_minor == 0)

1
src/amd/common/ac_perfcounter.c
View file

@ -726,6 +726,7 @@ bool ac_init_perfcounters(const struct radeon_info *info,
break;
case GFX11:
case GFX11_5:
case GFX11_7:
blocks = ac_gfx11_get_perfcounters(&num_blocks);
break;
case GFX12:

7
src/amd/common/ac_rgp.c
View file

@ -271,6 +271,7 @@ enum sqtt_gfxip_level
SQTT_GFXIP_LEVEL_GFXIP_11_0 = 0xc,
SQTT_GFXIP_LEVEL_GFXIP_11_5 = 0xd,
SQTT_GFXIP_LEVEL_GFXIP_12 = 0x10,
SQTT_GFXIP_LEVEL_GFXIP_11_7 = 0x11,
};
enum sqtt_memory_type
@ -364,6 +365,8 @@ static enum sqtt_gfxip_level ac_gfx_level_to_sqtt_gfxip_level(enum amd_gfx_level
return SQTT_GFXIP_LEVEL_GFXIP_11_0;
case GFX11_5:
return SQTT_GFXIP_LEVEL_GFXIP_11_5;
case GFX11_7:
return SQTT_GFXIP_LEVEL_GFXIP_11_7;
case GFX12:
return SQTT_GFXIP_LEVEL_GFXIP_12;
default:
@ -713,6 +716,7 @@ static enum sqtt_version ac_gfx_level_to_sqtt_version(enum amd_gfx_level gfx_lev
return SQTT_VERSION_2_4;
case GFX11:
case GFX11_5:
case GFX11_7:
return SQTT_VERSION_3_2;
case GFX12:
return SQTT_VERSION_3_3;
@ -860,6 +864,7 @@ enum elf_gfxip_level
EF_AMDGPU_MACH_AMDGCN_GFX1030 = 0x036,
EF_AMDGPU_MACH_AMDGCN_GFX1100 = 0x041,
EF_AMDGPU_MACH_AMDGCN_GFX1150 = 0x043,
EF_AMDGPU_MACH_AMDGCN_GFX1170 = 0x05d,
EF_AMDGPU_MACH_AMDGCN_GFX1200 = 0x04e,
};
@ -878,6 +883,8 @@ static enum elf_gfxip_level ac_gfx_level_to_elf_gfxip_level(enum amd_gfx_level g
return EF_AMDGPU_MACH_AMDGCN_GFX1100;
case GFX11_5:
return EF_AMDGPU_MACH_AMDGCN_GFX1150;
case GFX11_7:
return EF_AMDGPU_MACH_AMDGCN_GFX1170;
case GFX12:
return EF_AMDGPU_MACH_AMDGCN_GFX1200;
default:

8
src/amd/common/ac_shadowed_regs.c
View file

@ -735,7 +735,7 @@ void ac_get_reg_ranges(enum amd_gfx_level gfx_level, enum radeon_family family,
switch (type) {
case SI_REG_RANGE_UCONFIG:
if (gfx_level == GFX11 || gfx_level == GFX11_5)
if (gfx_level >= GFX11 && gfx_level < GFX12)
RETURN(Gfx11UserConfigShadowRange);
else if (gfx_level == GFX10_3)
RETURN(Gfx103UserConfigShadowRange);
@ -745,7 +745,7 @@ void ac_get_reg_ranges(enum amd_gfx_level gfx_level, enum radeon_family family,
RETURN(Gfx9UserConfigShadowRange);
break;
case SI_REG_RANGE_CONTEXT:
if (gfx_level == GFX11 || gfx_level == GFX11_5)
if (gfx_level >= GFX11 && gfx_level < GFX12)
RETURN(Gfx11ContextShadowRange);
else if (gfx_level == GFX10_3)
RETURN(Gfx103ContextShadowRange);
@ -755,7 +755,7 @@ void ac_get_reg_ranges(enum amd_gfx_level gfx_level, enum radeon_family family,
RETURN(Gfx9ContextShadowRange);
break;
case SI_REG_RANGE_SH:
if (gfx_level == GFX11 || gfx_level == GFX11_5)
if (gfx_level >= GFX11 && gfx_level < GFX12)
RETURN(Gfx11ShShadowRange);
else if (gfx_level == GFX10_3 || gfx_level == GFX10)
RETURN(Gfx10ShShadowRange);
@ -765,7 +765,7 @@ void ac_get_reg_ranges(enum amd_gfx_level gfx_level, enum radeon_family family,
RETURN(Gfx9ShShadowRange);
break;
case SI_REG_RANGE_CS_SH:
if (gfx_level == GFX11 || gfx_level == GFX11_5)
if (gfx_level >= GFX11 && gfx_level < GFX12)
RETURN(Gfx11CsShShadowRange);
else if (gfx_level == GFX10_3 || gfx_level == GFX10)
RETURN(Gfx10CsShShadowRange);

5
src/amd/common/ac_spm.c
View file

@ -678,6 +678,7 @@ bool ac_init_spm(const struct radeon_info *info,
break;
case GFX11:
case GFX11_5:
case GFX11_7:
create_info_count = ARRAY_SIZE(gfx11_spm_counters);
create_info = gfx11_spm_counters;
break;
@ -794,9 +795,9 @@ bool ac_init_spm(const struct radeon_info *info,
/* Configure the sample interval to default to 4096 clk. */
spm->sample_interval = 4096;
/* On GFX11-11.5, the data size written by the hw is in units of segment. */
/* On GFX11-11.7, the data size written by the hw is in units of segment. */
spm->ptr_granularity =
(info->gfx_level == GFX11 || info->gfx_level == GFX11_5) ? 32 : 1;
(info->gfx_level >= GFX11 && info->gfx_level < GFX12) ? 32 : 1;
return true;
}

11
src/amd/common/ac_surface.c
View file

@ -306,6 +306,7 @@ bool ac_is_modifier_supported(const struct radeon_info *info,
break;
case GFX11:
case GFX11_5:
case GFX11_7:
allowed_swizzles = ac_modifier_has_dcc(modifier) ? 0x88000000 : 0xCC440440;
break;
case GFX12:
@ -532,7 +533,8 @@ bool ac_get_supported_modifiers(const struct radeon_info *info,
break;
}
case GFX11:
case GFX11_5: {
case GFX11_5:
case GFX11_7: {
/* GFX11 has new microblock organization. No S modes for 2D. */
unsigned pipe_xor_bits_4k = MIN2(pipes, block_size_bits_4k - 8);
unsigned pipe_xor_bits_64k = MIN2(pipes, block_size_bits_64k - 8);
@ -593,7 +595,7 @@ bool ac_get_supported_modifiers(const struct radeon_info *info,
*/
/* Add the best non-displayable modifier first. */
if (info->gfx_level == GFX11_5)
if (info->gfx_level == GFX11_5 || info->gfx_level == GFX11_7)
ADD_MOD(modifier_dcc_best_gfx11_5 | AMD_FMT_MOD_SET(DCC_PIPE_ALIGN, 1));
ADD_MOD(modifier_dcc_best | AMD_FMT_MOD_SET(DCC_PIPE_ALIGN, 1));
@ -2051,6 +2053,7 @@ static bool is_dcc_supported_by_CB(const struct radeon_info *info, unsigned sw_m
case GFX11:
case GFX11_5:
case GFX11_7:
return sw_mode == ADDR_SW_64KB_Z_X || sw_mode == ADDR_SW_64KB_R_X ||
sw_mode == ADDR_SW_256KB_Z_X || sw_mode == ADDR_SW_256KB_R_X;
@ -2152,6 +2155,7 @@ static bool gfx9_is_dcc_supported_by_DCN(const struct radeon_info *info,
case GFX10_3:
case GFX11:
case GFX11_5:
case GFX11_7:
/* DCN requires INDEPENDENT_128B_BLOCKS = 0 only on Navi1x. */
if (info->gfx_level == GFX10 && surf->u.gfx9.color.dcc.independent_128B_blocks)
return false;
@ -3747,6 +3751,7 @@ void ac_compute_surface_modifier(const struct radeon_info *info,
break;
case GFX11:
case GFX11_5:
case GFX11_7:
version = AMD_FMT_MOD_TILE_VER_GFX11;
break;
case GFX12:
@ -4136,6 +4141,7 @@ bool ac_surface_apply_umd_metadata(const struct radeon_info *info, struct radeon
case GFX10_3:
case GFX11:
case GFX11_5:
case GFX11_7:
surf->meta_offset =
((uint64_t)G_00A018_META_DATA_ADDRESS_LO(desc[6]) << 8) | ((uint64_t)desc[7] << 16);
surf->u.gfx9.color.dcc.pipe_aligned = G_00A018_META_PIPE_ALIGNED(desc[6]);
@ -4183,6 +4189,7 @@ void ac_surface_compute_umd_metadata(const struct radeon_info *info, const struc
case GFX10_3:
case GFX11:
case GFX11_5:
case GFX11_7:
desc[6] &= C_00A018_META_DATA_ADDRESS_LO;
desc[6] |= S_00A018_META_DATA_ADDRESS_LO(surf->meta_offset >> 8);
desc[7] = surf->meta_offset >> 16;

1
src/amd/common/nir/ac_nir_meta_cs_blit.c
View file

@ -670,6 +670,7 @@ ac_prepare_compute_blit(const struct ac_cs_blit_options *options,
case GFX11:
case GFX11_5:
case GFX11_7:
/* Verified on Navi31. */
if (is_resolve) {
if (!((blit->dst.surf->bpe <= 2 && src_samples == 2) ||

1
src/amd/common/nir/ac_nir_meta_cs_clear_copy_buffer.c
View file

@ -490,6 +490,7 @@ ac_prepare_cs_clear_copy_buffer(const struct ac_cs_clear_copy_buffer_options *op
case GFX10_3:
case GFX11:
case GFX11_5:
case GFX11_7:
/* Optimal for Navi31, Navi21, Navi10. */
break;

8
src/gallium/winsys/amdgpu/drm/amdgpu_cs.cpp
View file

@ -1485,7 +1485,7 @@ static void amdgpu_cs_add_userq_packets(struct amdgpu_winsys *aws,
if (userq->ip_type == AMD_IP_GFX || userq->ip_type == AMD_IP_COMPUTE) {
struct cond_exec_skip_count *cond_exec_skip_counts = NULL;
if (csc->aws->info.gfx_level == GFX11_5 && userq->ip_type == AMD_IP_GFX) {
if ((csc->aws->info.gfx_level == GFX11_5 || csc->aws->info.gfx_level == GFX11_7) && userq->ip_type == AMD_IP_GFX) {
/* index 0 holds skip count for skipping the entire job. Rest for FENCE_WAIT_MULTI
* packet pre-emption going to end of the job.
*/
@ -1523,7 +1523,8 @@ static void amdgpu_cs_add_userq_packets(struct amdgpu_winsys *aws,
amdgpu_pkt_add_dw(fence_info[i + j].value >> 32);
}
if (csc->aws->info.gfx_level == GFX11_5 && userq->ip_type == AMD_IP_GFX) {
if ((csc->aws->info.gfx_level == GFX11_5 || csc->aws->info.gfx_level == GFX11_7) &&
userq->ip_type == AMD_IP_GFX) {
amdgpu_pkt_add_dw(PKT3(PKT3_COND_EXEC, 3, 0));
amdgpu_pkt_add_dw(0);
amdgpu_pkt_add_dw(0);
@ -1594,7 +1595,8 @@ static void amdgpu_cs_add_userq_packets(struct amdgpu_winsys *aws,
amdgpu_pkt_add_dw(PKT3(PKT3_PROTECTED_FENCE_SIGNAL, 0, 0));
amdgpu_pkt_add_dw(0);
if (csc->aws->info.gfx_level == GFX11_5 && userq->ip_type == AMD_IP_GFX) {
if ((csc->aws->info.gfx_level == GFX11_5 || csc->aws->info.gfx_level == GFX11_7) &&
userq->ip_type == AMD_IP_GFX) {
for (unsigned i = 0; i < 1 + DIV_ROUND_UP(num_fences, 4); i++)
*cond_exec_skip_counts[i].count_dw_ptr = (amdgpu_pkt_get_next_wptr() -
cond_exec_skip_counts[i].start_wptr) |