fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-20 07:20:10 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

anv: remove CS-L3 coherency on Xe2
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
Details
macOS-CI / macOS-CI (xlib) (push) Waiting to run
Details

Browse source 
I'll try to write some crucible tests for this.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: be5f5f659f ("anv: consider CS coherent with L3 on Xe2+")
Fixes: 503355c7f8 ("anv: update pipeline barriers for Xe2+")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38966>
This commit is contained in:
Lionel Landwerlin 2025-12-16 10:23:22 +02:00 • committed by Marge Bot
parent 10f259e673
commit d99a3d9b58
2 changed files with 5 additions and 7 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/intel/vulkan/anv_private.h
View file

@ -4061,7 +4061,7 @@ enum anv_query_bits {
* there is no tile cache. * there is no tile cache.
*/ */
#define ANV_DEVINFO_HAS_COHERENT_L3_CS(devinfo) \ #define ANV_DEVINFO_HAS_COHERENT_L3_CS(devinfo) \
(intel_device_info_is_dg2(devinfo) || (devinfo)->ver >= 20) (intel_device_info_is_dg2(devinfo))
/* Things we need to flush before accessing query data using the command /* Things we need to flush before accessing query data using the command
* streamer. * streamer.

6
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -4518,13 +4518,11 @@ anv_pipe_invalidate_bits_for_access_flags(struct anv_cmd_buffer *cmd_buffer,
* an A64 message, so we need to invalidate constant cache. * an A64 message, so we need to invalidate constant cache.
*/ */
pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT; pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
/* Prior to Gfx20, Tile & Data cache flush needed For Cmd*Indirect* /* Tile & Data cache flush needed For Cmd*Indirect* commands since
* commands since command streamer is not L3 coherent. * command streamer is not L3 coherent.
*/ */
if (device->info->ver < 20) {
pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT | pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT |
ANV_PIPE_TILE_CACHE_FLUSH_BIT; ANV_PIPE_TILE_CACHE_FLUSH_BIT;
}
break; break;
case VK_ACCESS_2_INDEX_READ_BIT: case VK_ACCESS_2_INDEX_READ_BIT:
case VK_ACCESS_2_VERTEX_ATTRIBUTE_READ_BIT: case VK_ACCESS_2_VERTEX_ATTRIBUTE_READ_BIT: