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anv: consider CS coherent with L3 on Xe2+

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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38707>
This commit is contained in:
Lionel Landwerlin 2025-12-11 12:36:20 +02:00 • committed by Marge Bot
parent 503355c7f8
commit be5f5f659f
1 changed files with 8 additions and 7 deletions
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15
src/intel/vulkan/anv_private.h
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@ -4035,20 +4035,21 @@ enum anv_query_bits {
ANV_QUERY_WRITES_DATA_FLUSH = (1 << 3),
};
/* It's not clear why DG2 doesn't have issues with L3/CS coherency. But it's
* likely related to performance workaround 14015868140.
/* It's not clear why DG2/Xe2+ doesn't have issues with L3/CS coherency. But
* it's likely related to performance workaround 14015868140.
*
* For now we enable this only on DG2 and platform prior to Gfx12 where there
* is no tile cache.
* For now we enable this only on DG2/Xe2+ and platform prior to Gfx12 where
* there is no tile cache.
*/
#define ANV_DEVINFO_HAS_COHERENT_L3_CS(devinfo) \
(intel_device_info_is_dg2(devinfo))
(intel_device_info_is_dg2(devinfo) || (devinfo)->ver >= 20)
/* Things we need to flush before accessing query data using the command
* streamer.
*
* Prior to DG2 experiments show that the command streamer is not coherent
* with the tile cache so we need to flush it to make any data visible to CS.
* Prior to DG2/Xe2+ experiments show that the command streamer is not
* coherent with the tile cache so we need to flush it to make any data
* visible to CS.
*
* Otherwise we want to flush the RT cache which is where blorp writes, either
* for clearing the query buffer or for clearing the destination buffer in