diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 9ee41c0db20..eac297fd34a 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -4061,7 +4061,7 @@ enum anv_query_bits {
  * there is no tile cache.
  */
 #define ANV_DEVINFO_HAS_COHERENT_L3_CS(devinfo) \
-   (intel_device_info_is_dg2(devinfo) || (devinfo)->ver >= 20)
+   (intel_device_info_is_dg2(devinfo))
 
 /* Things we need to flush before accessing query data using the command
  * streamer.
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index 74c79e3c927..da858269296 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -4518,13 +4518,11 @@ anv_pipe_invalidate_bits_for_access_flags(struct anv_cmd_buffer *cmd_buffer,
           * an A64 message, so we need to invalidate constant cache.
           */
          pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
-         /* Prior to Gfx20, Tile & Data cache flush needed For Cmd*Indirect*
-          * commands since command streamer is not L3 coherent.
+         /* Tile & Data cache flush needed For Cmd*Indirect* commands since
+          * command streamer is not L3 coherent.
           */
-         if (device->info->ver < 20) {
-            pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT |
-                         ANV_PIPE_TILE_CACHE_FLUSH_BIT;
-         }
+         pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT |
+                      ANV_PIPE_TILE_CACHE_FLUSH_BIT;
          break;
       case VK_ACCESS_2_INDEX_READ_BIT:
       case VK_ACCESS_2_VERTEX_ATTRIBUTE_READ_BIT: