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radeonsi: disable binning correctly on gfx11.5

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Fixes: b44a886b84 - amd/common: add registers for gfx11.5

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27943>
(cherry picked from commit 20445f296b)
This commit is contained in:
Marek Olšák 2024-02-26 21:08:51 -05:00 • committed by Eric Engestrom
parent 724b1c197d
commit d5b22fa737
2 changed files with 5 additions and 2 deletions
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2
.pick_status.json
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@ -1594,7 +1594,7 @@
"description": "radeonsi: disable binning correctly on gfx11.5",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "b44a886b84c91320f170bd108213768bb47ff6a3",
"notes": null

5
src/gallium/drivers/radeonsi/si_state_binning.c
View file

@ -393,6 +393,9 @@ static void si_emit_dpbb_disable(struct si_context *sctx)
if (sctx->gfx_level >= GFX10) {
struct uvec2 bin_size = {};
struct uvec2 bin_size_extend = {};
unsigned binning_disabled =
sctx->gfx_level >= GFX11_5 ? V_028C44_BINNING_DISABLED
: V_028C44_DISABLE_BINNING_USE_NEW_SC;
bin_size.x = 128;
bin_size.y = sctx->framebuffer.min_bytes_per_pixel <= 4 ? 128 : 64;
@ -404,7 +407,7 @@ static void si_emit_dpbb_disable(struct si_context *sctx)
radeon_opt_set_context_reg(sctx, R_028C44_PA_SC_BINNER_CNTL_0,
SI_TRACKED_PA_SC_BINNER_CNTL_0,
S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) |
S_028C44_BINNING_MODE(binning_disabled) |
S_028C44_BIN_SIZE_X(bin_size.x == 16) |
S_028C44_BIN_SIZE_Y(bin_size.y == 16) |
S_028C44_BIN_SIZE_X_EXTEND(bin_size_extend.x) |