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radeonsi: ensure TC_L2_dirty is set if we don't sync after internal SSBO blits
There was a case where if we don't sync, we wouldn't set TC_L2_dirty either, which could cause problems later. Fixes:f703dfd1bb- radeonsi: add gfx12 Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30503> (cherry picked from commitebc5116e70)
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parent
4b7fda129e
commit
d05e39f304
2 changed files with 4 additions and 6 deletions
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@ -664,7 +664,7 @@
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"description": "radeonsi: ensure TC_L2_dirty is set if we don't sync after internal SSBO blits",
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"nominated": true,
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"nomination_type": 1,
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"resolution": 0,
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"resolution": 1,
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"main_sha": null,
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"because_sha": "f703dfd1bb8c22b6791dd95c7de270e176452b4b",
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"notes": null
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@ -187,11 +187,9 @@ void si_launch_grid_internal_ssbos(struct si_context *sctx, struct pipe_grid_inf
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si_launch_grid_internal(sctx, info, shader, flags);
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/* Do cache flushing at the end. */
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if (get_cache_policy(sctx, coher, 0) == L2_BYPASS) {
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if (flags & SI_OP_SYNC_AFTER) {
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sctx->flags |= SI_CONTEXT_WB_L2;
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si_mark_atom_dirty(sctx, &sctx->atoms.s.cache_flush);
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}
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if (flags & SI_OP_SYNC_AFTER && get_cache_policy(sctx, coher, 0) == L2_BYPASS) {
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sctx->flags |= SI_CONTEXT_WB_L2;
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si_mark_atom_dirty(sctx, &sctx->atoms.s.cache_flush);
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} else {
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while (writeable_bitmask)
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si_resource(buffers[u_bit_scan(&writeable_bitmask)].buffer)->TC_L2_dirty = true;
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