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radeonsi: ensure TC_L2_dirty is set if we don't sync after internal SSBO blits

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There was a case where if we don't sync, we wouldn't set TC_L2_dirty either,
which could cause problems later.

Fixes: f703dfd1bb - radeonsi: add gfx12

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30503>
This commit is contained in:
Marek Olšák 2024-07-30 16:10:45 -04:00 • committed by Marge Bot
parent e4b3848fde
commit ebc5116e70
1 changed files with 3 additions and 5 deletions
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8
src/gallium/drivers/radeonsi/si_compute_blit.c
View file

@ -187,11 +187,9 @@ void si_launch_grid_internal_ssbos(struct si_context *sctx, struct pipe_grid_inf
si_launch_grid_internal(sctx, info, shader, flags);
/* Do cache flushing at the end. */
if (get_cache_policy(sctx, coher, 0) == L2_BYPASS) {
if (flags & SI_OP_SYNC_AFTER) {
sctx->flags |= SI_CONTEXT_WB_L2;
si_mark_atom_dirty(sctx, &sctx->atoms.s.cache_flush);
}
if (flags & SI_OP_SYNC_AFTER && get_cache_policy(sctx, coher, 0) == L2_BYPASS) {
sctx->flags |= SI_CONTEXT_WB_L2;
si_mark_atom_dirty(sctx, &sctx->atoms.s.cache_flush);
} else {
while (writeable_bitmask)
si_resource(buffers[u_bit_scan(&writeable_bitmask)].buffer)->TC_L2_dirty = true;