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tu: handle DS_DEPTH_BOUNDS_TEST_BOUNDS state under TU_DYNAMIC_STATE_RB_DEPTH_CNTL

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MESA_VK_DYNAMIC_DS_DEPTH_BOUNDS_TEST_BOUNDS state should be emitted as part
of TU_DYNAMIC_STATE_RB_DEPTH_CNTL along with other depth state, and not as
part of dynamic stencil state.

Signed-off-by: Zan Dobersek <zdobersek@igalia.com>
Fixes: 979cf7bac0 ("tu: Merge depth/stencil draw states")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39323>
(cherry picked from commit 3cb4776ede)
This commit is contained in:
Zan Dobersek 2026-01-21 13:05:55 +01:00 • committed by Eric Engestrom
parent 6c6ed2a9e6
commit cfdaa05349
2 changed files with 10 additions and 8 deletions
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2
.pick_status.json
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@ -2614,7 +2614,7 @@
"description": "tu: handle DS_DEPTH_BOUNDS_TEST_BOUNDS state under TU_DYNAMIC_STATE_RB_DEPTH_CNTL",
"nominated": true,
"nomination_type": 2,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "979cf7bac04fd833c13407b98851e7a4f15d8d33",
"notes": null

16
src/freedreno/vulkan/tu_pipeline.cc
View file

@ -3556,7 +3556,6 @@ static const enum mesa_vk_dynamic_graphics_state tu_ds_state[] = {
MESA_VK_DYNAMIC_DS_STENCIL_COMPARE_MASK,
MESA_VK_DYNAMIC_DS_STENCIL_WRITE_MASK,
MESA_VK_DYNAMIC_DS_STENCIL_REFERENCE,
MESA_VK_DYNAMIC_DS_DEPTH_BOUNDS_TEST_BOUNDS,
};
template <chip CHIP>
@ -3565,7 +3564,7 @@ tu6_ds_size(struct tu_device *dev,
const struct vk_depth_stencil_state *ds,
const struct vk_render_pass_state *rp)
{
return 13;
return 10;
}
template <chip CHIP>
@ -3615,10 +3614,6 @@ tu6_emit_ds(struct tu_cs *cs,
tu_cs_emit_regs(cs, A6XX_RB_STENCIL_REF_CNTL(
.ref = ds->stencil.front.reference,
.bfref = ds->stencil.back.reference));
tu_cs_emit_regs(cs,
A6XX_RB_DEPTH_BOUND_MIN(ds->depth.bounds_test.min),
A6XX_RB_DEPTH_BOUND_MAX(ds->depth.bounds_test.max));
}
static const enum mesa_vk_dynamic_graphics_state tu_rb_depth_cntl_state[] = {
@ -3626,6 +3621,7 @@ static const enum mesa_vk_dynamic_graphics_state tu_rb_depth_cntl_state[] = {
MESA_VK_DYNAMIC_DS_DEPTH_WRITE_ENABLE,
MESA_VK_DYNAMIC_DS_DEPTH_COMPARE_OP,
MESA_VK_DYNAMIC_DS_DEPTH_BOUNDS_TEST_ENABLE,
MESA_VK_DYNAMIC_DS_DEPTH_BOUNDS_TEST_BOUNDS,
MESA_VK_DYNAMIC_RS_DEPTH_CLAMP_ENABLE,
};
@ -3636,7 +3632,7 @@ tu6_rb_depth_cntl_size(struct tu_device *dev,
const struct vk_render_pass_state *rp,
const struct vk_rasterization_state *rs)
{
return 4;
return 7;
}
template <chip CHIP>
@ -3676,9 +3672,15 @@ tu6_emit_rb_depth_cntl(struct tu_cs *cs,
.o_depth_01_clamp_en = CHIP >= A8XX,
));
tu_cs_emit_regs(cs, GRAS_SU_DEPTH_CNTL(CHIP, depth_test));
tu_cs_emit_regs(cs,
A6XX_RB_DEPTH_BOUND_MIN(ds->depth.bounds_test.min),
A6XX_RB_DEPTH_BOUND_MAX(ds->depth.bounds_test.max));
} else {
tu_cs_emit_regs(cs, A6XX_RB_DEPTH_CNTL());
tu_cs_emit_regs(cs, GRAS_SU_DEPTH_CNTL(CHIP));
tu_cs_emit_regs(cs,
A6XX_RB_DEPTH_BOUND_MIN(),
A6XX_RB_DEPTH_BOUND_MAX());
}
}