From cfdaa05349217d6830d7897921aacf453c46f5cd Mon Sep 17 00:00:00 2001
From: Zan Dobersek <zdobersek@igalia.com>
Date: Wed, 21 Jan 2026 13:05:55 +0100
Subject: [PATCH] tu: handle DS_DEPTH_BOUNDS_TEST_BOUNDS state under
 TU_DYNAMIC_STATE_RB_DEPTH_CNTL

MESA_VK_DYNAMIC_DS_DEPTH_BOUNDS_TEST_BOUNDS state should be emitted as part
of TU_DYNAMIC_STATE_RB_DEPTH_CNTL along with other depth state, and not as
part of dynamic stencil state.

Signed-off-by: Zan Dobersek <zdobersek@igalia.com>
Fixes: 979cf7bac04 ("tu: Merge depth/stencil draw states")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39323>
(cherry picked from commit 3cb4776ede401827fc64d12c7b849ec37b625860)
---
 .pick_status.json                   |  2 +-
 src/freedreno/vulkan/tu_pipeline.cc | 16 +++++++++-------
 2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index f8d7ffb0b74..e1db9508bc9 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -2614,7 +2614,7 @@
         "description": "tu: handle DS_DEPTH_BOUNDS_TEST_BOUNDS state under TU_DYNAMIC_STATE_RB_DEPTH_CNTL",
         "nominated": true,
         "nomination_type": 2,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": "979cf7bac04fd833c13407b98851e7a4f15d8d33",
         "notes": null
diff --git a/src/freedreno/vulkan/tu_pipeline.cc b/src/freedreno/vulkan/tu_pipeline.cc
index 9c7e51556fd..c3e1cba82ad 100644
--- a/src/freedreno/vulkan/tu_pipeline.cc
+++ b/src/freedreno/vulkan/tu_pipeline.cc
@@ -3556,7 +3556,6 @@ static const enum mesa_vk_dynamic_graphics_state tu_ds_state[] = {
    MESA_VK_DYNAMIC_DS_STENCIL_COMPARE_MASK,
    MESA_VK_DYNAMIC_DS_STENCIL_WRITE_MASK,
    MESA_VK_DYNAMIC_DS_STENCIL_REFERENCE,
-   MESA_VK_DYNAMIC_DS_DEPTH_BOUNDS_TEST_BOUNDS,
 };
 
 template <chip CHIP>
@@ -3565,7 +3564,7 @@ tu6_ds_size(struct tu_device *dev,
                  const struct vk_depth_stencil_state *ds,
                  const struct vk_render_pass_state *rp)
 {
-   return 13;
+   return 10;
 }
 
 template <chip CHIP>
@@ -3615,10 +3614,6 @@ tu6_emit_ds(struct tu_cs *cs,
    tu_cs_emit_regs(cs, A6XX_RB_STENCIL_REF_CNTL(
       .ref = ds->stencil.front.reference,
       .bfref = ds->stencil.back.reference));
-
-   tu_cs_emit_regs(cs,
-                   A6XX_RB_DEPTH_BOUND_MIN(ds->depth.bounds_test.min),
-                   A6XX_RB_DEPTH_BOUND_MAX(ds->depth.bounds_test.max));
 }
 
 static const enum mesa_vk_dynamic_graphics_state tu_rb_depth_cntl_state[] = {
@@ -3626,6 +3621,7 @@ static const enum mesa_vk_dynamic_graphics_state tu_rb_depth_cntl_state[] = {
    MESA_VK_DYNAMIC_DS_DEPTH_WRITE_ENABLE,
    MESA_VK_DYNAMIC_DS_DEPTH_COMPARE_OP,
    MESA_VK_DYNAMIC_DS_DEPTH_BOUNDS_TEST_ENABLE,
+   MESA_VK_DYNAMIC_DS_DEPTH_BOUNDS_TEST_BOUNDS,
    MESA_VK_DYNAMIC_RS_DEPTH_CLAMP_ENABLE,
 };
 
@@ -3636,7 +3632,7 @@ tu6_rb_depth_cntl_size(struct tu_device *dev,
                        const struct vk_render_pass_state *rp,
                        const struct vk_rasterization_state *rs)
 {
-   return 4;
+   return 7;
 }
 
 template <chip CHIP>
@@ -3676,9 +3672,15 @@ tu6_emit_rb_depth_cntl(struct tu_cs *cs,
          .o_depth_01_clamp_en = CHIP >= A8XX,
       ));
       tu_cs_emit_regs(cs, GRAS_SU_DEPTH_CNTL(CHIP, depth_test));
+      tu_cs_emit_regs(cs,
+                      A6XX_RB_DEPTH_BOUND_MIN(ds->depth.bounds_test.min),
+                      A6XX_RB_DEPTH_BOUND_MAX(ds->depth.bounds_test.max));
    } else {
       tu_cs_emit_regs(cs, A6XX_RB_DEPTH_CNTL());
       tu_cs_emit_regs(cs, GRAS_SU_DEPTH_CNTL(CHIP));
+      tu_cs_emit_regs(cs,
+                      A6XX_RB_DEPTH_BOUND_MIN(),
+                      A6XX_RB_DEPTH_BOUND_MAX());
    }
 }