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radv: re-disable TC-compat HTILE for D32S8 on all generations

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This actually introduced some VRS related regressions and some others.

Fixes: cc5b6a0e89 ("radv: enable TC-compat HTILE with D32S8 and MSAA on GFX9+")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8777>
This commit is contained in:
Samuel Pitoiset 2021-01-29 12:14:18 +01:00
parent 97c3ec6116
commit c092ff2f2f
1 changed files with 6 additions and 6 deletions
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12
src/amd/vulkan/radv_image.c
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@ -95,13 +95,13 @@ radv_use_tc_compat_htile_for_image(struct radv_device *device,
VK_IMAGE_USAGE_TRANSFER_SRC_BIT)))
return false;
if (device->physical_device->rad_info.chip_class < GFX9) {
/* FIXME: for some reason TC compat with 2/4/8 samples breaks
* some cts tests - disable for now.
*/
if (pCreateInfo->samples >= 2 && format == VK_FORMAT_D32_SFLOAT_S8_UINT)
return false;
/* FIXME: for some reason TC compat with 2/4/8 samples breaks
* some cts tests - disable for now.
*/
if (pCreateInfo->samples >= 2 && format == VK_FORMAT_D32_SFLOAT_S8_UINT)
return false;
if (device->physical_device->rad_info.chip_class < GFX9) {
/* GFX9+ supports compression for both 32-bit and 16-bit depth
* surfaces, while GFX8 only supports 32-bit natively. Though,
* the driver allows TC-compat HTILE for 16-bit depth surfaces