From c092ff2f2f57a4cc559507420f7f49eaf9b1d8ab Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Fri, 29 Jan 2021 12:14:18 +0100 Subject: [PATCH] radv: re-disable TC-compat HTILE for D32S8 on all generations This actually introduced some VRS related regressions and some others. Fixes: cc5b6a0e897 ("radv: enable TC-compat HTILE with D32S8 and MSAA on GFX9+") Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/vulkan/radv_image.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index 0229db314c0..94a55b46ed9 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -95,13 +95,13 @@ radv_use_tc_compat_htile_for_image(struct radv_device *device, VK_IMAGE_USAGE_TRANSFER_SRC_BIT))) return false; - if (device->physical_device->rad_info.chip_class < GFX9) { - /* FIXME: for some reason TC compat with 2/4/8 samples breaks - * some cts tests - disable for now. - */ - if (pCreateInfo->samples >= 2 && format == VK_FORMAT_D32_SFLOAT_S8_UINT) - return false; + /* FIXME: for some reason TC compat with 2/4/8 samples breaks + * some cts tests - disable for now. + */ + if (pCreateInfo->samples >= 2 && format == VK_FORMAT_D32_SFLOAT_S8_UINT) + return false; + if (device->physical_device->rad_info.chip_class < GFX9) { /* GFX9+ supports compression for both 32-bit and 16-bit depth * surfaces, while GFX8 only supports 32-bit natively. Though, * the driver allows TC-compat HTILE for 16-bit depth surfaces