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intel/isl: Allow HiZ with Tile4/64 surfaces

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Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14091>
This commit is contained in:
Nanley Chery 2019-05-03 17:40:54 -07:00 • committed by Marge Bot
parent 50967402cc
commit b77d694223
2 changed files with 9 additions and 4 deletions
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4
src/intel/isl/isl.c
View file

@ -1983,10 +1983,6 @@ isl_surf_get_hiz_surf(const struct isl_device *dev,
if (!isl_surf_usage_is_depth(surf->usage))
return false;
/* HiZ only works with Y-tiled depth buffers */
if (!isl_tiling_is_any_y(surf->tiling))
return false;
/* On SNB+, compressed depth buffers cannot be interleaved with stencil. */
switch (surf->format) {
case ISL_FORMAT_R24_UNORM_X8_TYPELESS:

9
src/intel/isl/isl_emit_depth_stencil.c
View file

@ -153,6 +153,15 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
if (separate_stencil || info->hiz_usage == ISL_AUX_USAGE_HIZ) {
assert(ISL_DEV_USE_SEPARATE_STENCIL(dev));
db.SeparateStencilBufferEnable = true;
/* From the IronLake PRM, Vol 2 Part 1,
* 3DSTATE_DEPTH_BUFFER::Tiled Surface,
*
* When Hierarchical Depth Buffer is enabled, this bit must be set.
*
* HiZ only works on tiled depth buffers.
*/
assert(info->depth_surf->tiling != ISL_TILING_LINEAR);
db.HierarchicalDepthBufferEnable = true;
}
#endif