diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index d2c05a48514..9375ff9df33 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1983,10 +1983,6 @@ isl_surf_get_hiz_surf(const struct isl_device *dev,
    if (!isl_surf_usage_is_depth(surf->usage))
       return false;
 
-   /* HiZ only works with Y-tiled depth buffers */
-   if (!isl_tiling_is_any_y(surf->tiling))
-      return false;
-
    /* On SNB+, compressed depth buffers cannot be interleaved with stencil. */
    switch (surf->format) {
    case ISL_FORMAT_R24_UNORM_X8_TYPELESS:
diff --git a/src/intel/isl/isl_emit_depth_stencil.c b/src/intel/isl/isl_emit_depth_stencil.c
index fdb825acf4a..1bc9b72acb7 100644
--- a/src/intel/isl/isl_emit_depth_stencil.c
+++ b/src/intel/isl/isl_emit_depth_stencil.c
@@ -153,6 +153,15 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
    if (separate_stencil || info->hiz_usage == ISL_AUX_USAGE_HIZ) {
       assert(ISL_DEV_USE_SEPARATE_STENCIL(dev));
       db.SeparateStencilBufferEnable = true;
+
+      /* From the IronLake PRM, Vol 2 Part 1,
+       * 3DSTATE_DEPTH_BUFFER::Tiled Surface,
+       *
+       *    When Hierarchical Depth Buffer is enabled, this bit must be set.
+       *
+       * HiZ only works on tiled depth buffers.
+       */
+      assert(info->depth_surf->tiling != ISL_TILING_LINEAR);
       db.HierarchicalDepthBufferEnable = true;
    }
 #endif