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intel/fs: Map all TES input attributes to ATTR register number 0.

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Instead of treating fs_reg::nr as an offset for ATTR registers simply
consider different indices as denoting disjoint spaces that can never
be accessed simultaneously by a single region.  From now on geometry
stages will just use ATTR #0 for everything and select specific
attributes via offset() with the native dispatch width of the program,
which should work on current platforms as well as on Xe2+.  See
"intel/fs: Map all GS input attributes to ATTR register number 0." for
the rationale.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
This commit is contained in:
Francisco Jerez 2022-09-12 16:48:02 -07:00 • committed by Marge Bot
parent ef12565a37
commit b26cf8b189
1 changed files with 4 additions and 5 deletions
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9
src/intel/compiler/brw_fs_nir.cpp
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@ -3151,11 +3151,10 @@ fs_nir_emit_tes_intrinsic(nir_to_brw_state &ntb,
*/
const unsigned max_push_slots = 32;
if (imm_offset < max_push_slots) {
fs_reg src = fs_reg(ATTR, imm_offset / 2, dest.type);
for (int i = 0; i < instr->num_components; i++) {
unsigned comp = 4 * (imm_offset % 2) + i + first_component;
bld.MOV(offset(dest, bld, i), component(src, comp));
}
const fs_reg src = horiz_offset(fs_reg(ATTR, 0, dest.type),
4 * imm_offset + first_component);
for (int i = 0; i < instr->num_components; i++)
bld.MOV(offset(dest, bld, i), component(src, i));
tes_prog_data->base.urb_read_length =
MAX2(tes_prog_data->base.urb_read_length,