From b26cf8b1891b820da10c74eef9298a637e75a976 Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Mon, 12 Sep 2022 16:48:02 -0700 Subject: [PATCH] intel/fs: Map all TES input attributes to ATTR register number 0. Instead of treating fs_reg::nr as an offset for ATTR registers simply consider different indices as denoting disjoint spaces that can never be accessed simultaneously by a single region. From now on geometry stages will just use ATTR #0 for everything and select specific attributes via offset() with the native dispatch width of the program, which should work on current platforms as well as on Xe2+. See "intel/fs: Map all GS input attributes to ATTR register number 0." for the rationale. Reviewed-by: Caio Oliveira Part-of: --- src/intel/compiler/brw_fs_nir.cpp | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 9215b89ab6f..3cd6efd7592 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -3151,11 +3151,10 @@ fs_nir_emit_tes_intrinsic(nir_to_brw_state &ntb, */ const unsigned max_push_slots = 32; if (imm_offset < max_push_slots) { - fs_reg src = fs_reg(ATTR, imm_offset / 2, dest.type); - for (int i = 0; i < instr->num_components; i++) { - unsigned comp = 4 * (imm_offset % 2) + i + first_component; - bld.MOV(offset(dest, bld, i), component(src, comp)); - } + const fs_reg src = horiz_offset(fs_reg(ATTR, 0, dest.type), + 4 * imm_offset + first_component); + for (int i = 0; i < instr->num_components; i++) + bld.MOV(offset(dest, bld, i), component(src, i)); tes_prog_data->base.urb_read_length = MAX2(tes_prog_data->base.urb_read_length,