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intel/fs: Map all VS input attributes to ATTR register number 0.

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Instead of treating fs_reg::nr as an offset for ATTR registers simply
consider different indices as denoting disjoint spaces that can never
be accessed simultaneously by a single region.  From now on geometry
stages will just use ATTR #0 for everything and select specific
attributes via offset() with the native dispatch width of the program,
which should work on current platforms as well as on Xe2+.  See
"intel/fs: Map all GS input attributes to ATTR register number 0." for
the rationale.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
This commit is contained in:
Francisco Jerez 2022-09-12 16:47:19 -07:00 • committed by Marge Bot
parent 1d22721b5a
commit ef12565a37
1 changed files with 4 additions and 3 deletions
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7
src/intel/compiler/brw_fs_nir.cpp
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@ -2652,9 +2652,10 @@ fs_nir_emit_vs_intrinsic(nir_to_brw_state &ntb,
case nir_intrinsic_load_input: {
assert(instr->def.bit_size == 32);
fs_reg src = fs_reg(ATTR, nir_intrinsic_base(instr) * 4, dest.type);
src = offset(src, bld, nir_intrinsic_component(instr));
src = offset(src, bld, nir_src_as_uint(instr->src[0]));
const fs_reg src = offset(fs_reg(ATTR, 0, dest.type), bld,
nir_intrinsic_base(instr) * 4 +
nir_intrinsic_component(instr) +
nir_src_as_uint(instr->src[0]));
for (unsigned i = 0; i < instr->num_components; i++)
bld.MOV(offset(dest, bld, i), offset(src, bld, i));