fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-06 05:08:08 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

radv: fix compute shader invocations query on compute queue on GFX6

Browse source 
Looks like GFX6 always writes the number of compute shader invocations
at offset 0 when used on compute queue.

This fixes dEQP-VK.query_pool.statistics_query.*_cq on GFX6.

Fixes: a9945216ba ("radv: fix COMPUTE_SHADER_INVOCATIONS query on compute queue")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25957>
This commit is contained in:
Samuel Pitoiset 2023-10-30 12:50:56 +01:00 • committed by Marge Bot
parent 46dc02354a
commit 9a0a77cb53
1 changed files with 2 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
src/amd/vulkan/radv_query.c
View file

@ -1755,7 +1755,7 @@ emit_begin_query(struct radv_cmd_buffer *cmd_buffer, struct radv_query_pool *poo
radv_update_hw_pipelinestat(cmd_buffer);
if (cmd_buffer->qf == RADV_QUEUE_COMPUTE) {
if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
uint32_t cs_invoc_offset =
radv_get_pipelinestat_query_offset(VK_QUERY_PIPELINE_STATISTIC_COMPUTE_SHADER_INVOCATIONS_BIT);
va += cs_invoc_offset;
@ -1916,7 +1916,7 @@ emit_end_query(struct radv_cmd_buffer *cmd_buffer, struct radv_query_pool *pool,
va += pipelinestat_block_size;
if (cmd_buffer->qf == RADV_QUEUE_COMPUTE) {
if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
uint32_t cs_invoc_offset =
radv_get_pipelinestat_query_offset(VK_QUERY_PIPELINE_STATISTIC_COMPUTE_SHADER_INVOCATIONS_BIT);
va += cs_invoc_offset;