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radv: fix COMPUTE_SHADER_INVOCATIONS query on compute queue

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The VA needs to be adjusted, otherwise the hw always writes at offset 0.

This fixes dEQP-VK.query_pool.statistics_query.*_cq.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25406>
This commit is contained in:
Samuel Pitoiset 2023-09-26 18:19:59 +02:00 • committed by Marge Bot
parent c1b916ccb9
commit a9945216ba
1 changed files with 12 additions and 0 deletions
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12
src/amd/vulkan/radv_query.c
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@ -1736,6 +1736,12 @@ emit_begin_query(struct radv_cmd_buffer *cmd_buffer, struct radv_query_pool *poo
radv_update_hw_pipelinestat(cmd_buffer);
if (cmd_buffer->qf == RADV_QUEUE_COMPUTE) {
uint32_t cs_invoc_offset =
radv_get_pipelinestat_query_offset(VK_QUERY_PIPELINE_STATISTIC_COMPUTE_SHADER_INVOCATIONS_BIT);
va += cs_invoc_offset;
}
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
radeon_emit(cs, va);
@ -1886,6 +1892,12 @@ emit_end_query(struct radv_cmd_buffer *cmd_buffer, struct radv_query_pool *pool,
va += pipelinestat_block_size;
if (cmd_buffer->qf == RADV_QUEUE_COMPUTE) {
uint32_t cs_invoc_offset =
radv_get_pipelinestat_query_offset(VK_QUERY_PIPELINE_STATISTIC_COMPUTE_SHADER_INVOCATIONS_BIT);
va += cs_invoc_offset;
}
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
radeon_emit(cs, va);