From 9a0a77cb53d0d31c7a090d06ac905d69e9c1131c Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Mon, 30 Oct 2023 12:50:56 +0100 Subject: [PATCH] radv: fix compute shader invocations query on compute queue on GFX6 Looks like GFX6 always writes the number of compute shader invocations at offset 0 when used on compute queue. This fixes dEQP-VK.query_pool.statistics_query.*_cq on GFX6. Fixes: a9945216ba2 ("radv: fix COMPUTE_SHADER_INVOCATIONS query on compute queue") Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_query.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c index 7e43604c8bc..02339b508be 100644 --- a/src/amd/vulkan/radv_query.c +++ b/src/amd/vulkan/radv_query.c @@ -1755,7 +1755,7 @@ emit_begin_query(struct radv_cmd_buffer *cmd_buffer, struct radv_query_pool *poo radv_update_hw_pipelinestat(cmd_buffer); - if (cmd_buffer->qf == RADV_QUEUE_COMPUTE) { + if (radv_cmd_buffer_uses_mec(cmd_buffer)) { uint32_t cs_invoc_offset = radv_get_pipelinestat_query_offset(VK_QUERY_PIPELINE_STATISTIC_COMPUTE_SHADER_INVOCATIONS_BIT); va += cs_invoc_offset; @@ -1916,7 +1916,7 @@ emit_end_query(struct radv_cmd_buffer *cmd_buffer, struct radv_query_pool *pool, va += pipelinestat_block_size; - if (cmd_buffer->qf == RADV_QUEUE_COMPUTE) { + if (radv_cmd_buffer_uses_mec(cmd_buffer)) { uint32_t cs_invoc_offset = radv_get_pipelinestat_query_offset(VK_QUERY_PIPELINE_STATISTIC_COMPUTE_SHADER_INVOCATIONS_BIT); va += cs_invoc_offset;