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nvk: Fix cases where execution mode is specified in the tesc shader.

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We need to keep some context for the compilation of the tessellation shaders.
This is required in the case where the domain is specified in the
tessellation control shader instead of the tessellation evaluation
shader, as codegen needs the domain information when compiling the
tessellation evaluation shader.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24326>
This commit is contained in:
George Ouzounoudis 2023-04-14 14:47:38 +03:00 • committed by Marge Bot
parent 544aadc56b
commit 93369f1f96
5 changed files with 25 additions and 4 deletions
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3
src/nouveau/vulkan/nvk_compute_pipeline.c
View file

@ -190,8 +190,9 @@ nvk_compute_pipeline_create(struct nvk_device *device,
nvk_lower_nir(device, nir, &robustness, false, pipeline_layout);
struct nvk_pipeline_compilation_ctx ctx = { 0 };
result = nvk_compile_nir(pdevice, nir, NULL,
&pipeline->base.shaders[MESA_SHADER_COMPUTE]);
&pipeline->base.shaders[MESA_SHADER_COMPUTE], &ctx);
ralloc_free(nir);
if (result != VK_SUCCESS)
goto fail;

6
src/nouveau/vulkan/nvk_graphics_pipeline.c
View file

@ -253,6 +253,10 @@ nvk_graphics_pipeline_create(struct nvk_device *device,
state.rp->view_mask != 0, pipeline_layout);
}
struct nvk_pipeline_compilation_ctx ctx = {
.tesc_domain = MESA_PRIM_POINTS,
};
for (gl_shader_stage stage = 0; stage < MESA_SHADER_STAGES; stage++) {
if (nir[stage] == NULL)
continue;
@ -264,7 +268,7 @@ nvk_graphics_pipeline_create(struct nvk_device *device,
}
result = nvk_compile_nir(pdevice, nir[stage], fs_key,
&pipeline->base.shaders[stage]);
&pipeline->base.shaders[stage], &ctx);
ralloc_free(nir[stage]);
if (result != VK_SUCCESS)
goto fail;

5
src/nouveau/vulkan/nvk_pipeline.h
View file

@ -65,4 +65,9 @@ nvk_graphics_pipeline_create(struct nvk_device *device,
const VkAllocationCallbacks *pAllocator,
VkPipeline *pPipeline);
struct nvk_pipeline_compilation_ctx {
uint8_t tesc_domain; // MESA_PRIM_{POINTS, QUADS, TRIANGLES, LINES}
};
#endif

11
src/nouveau/vulkan/nvk_shader.c
View file

@ -1,6 +1,7 @@
#include "nvk_device.h"
#include "nvk_shader.h"
#include "nvk_physical_device.h"
#include "nvk_pipeline.h"
#include "nouveau_bo.h"
#include "nouveau_context.h"
@ -954,7 +955,8 @@ nvk_fill_transform_feedback_state(struct nir_shader *nir,
VkResult
nvk_compile_nir(struct nvk_physical_device *device, nir_shader *nir,
const struct nvk_fs_key *fs_key,
struct nvk_shader *shader)
struct nvk_shader *shader,
struct nvk_pipeline_compilation_ctx *ctx)
{
struct nv50_ir_prog_info *info;
struct nv50_ir_prog_info_out info_out = {};
@ -977,6 +979,9 @@ nvk_compile_nir(struct nvk_physical_device *device, nir_shader *nir,
info->io.auxCBSlot = 1;
info->io.uboInfoBase = 0;
info->io.drawInfoBase = 0;
if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
info->prop.tese.prespecified_domain = ctx->tesc_domain;
}
if (nir->info.stage == MESA_SHADER_COMPUTE) {
info->prop.cp.gridInfoBase = 0;
} else {
@ -1050,6 +1055,10 @@ nvk_compile_nir(struct nvk_physical_device *device, nir_shader *nir,
}
}
if (info->type == PIPE_SHADER_TESS_CTRL) {
ctx->tesc_domain = info_out.prop.tp.domain;
}
return VK_SUCCESS;
}

4
src/nouveau/vulkan/nvk_shader.h
View file

@ -11,6 +11,7 @@ struct vk_shader_module;
struct vk_pipeline_robustness_state;
struct nvk_device;
struct nvk_physical_device;
struct nvk_pipeline_compilation_ctx;
#define GF100_SHADER_HEADER_SIZE (20 * 4)
#define TU102_SHADER_HEADER_SIZE (32 * 4)
@ -125,7 +126,8 @@ nvk_lower_nir(struct nvk_device *device, nir_shader *nir,
VkResult
nvk_compile_nir(struct nvk_physical_device *device, nir_shader *nir,
const struct nvk_fs_key *fs_key,
struct nvk_shader *shader);
struct nvk_shader *shader,
struct nvk_pipeline_compilation_ctx *ctx);
VkResult
nvk_shader_upload(struct nvk_device *dev, struct nvk_shader *shader);