diff --git a/src/nouveau/vulkan/nvk_compute_pipeline.c b/src/nouveau/vulkan/nvk_compute_pipeline.c
index 4fdcb413f8c..b619e8bd36d 100644
--- a/src/nouveau/vulkan/nvk_compute_pipeline.c
+++ b/src/nouveau/vulkan/nvk_compute_pipeline.c
@@ -190,8 +190,9 @@ nvk_compute_pipeline_create(struct nvk_device *device,
 
    nvk_lower_nir(device, nir, &robustness, false, pipeline_layout);
 
+   struct nvk_pipeline_compilation_ctx ctx = { 0 };
    result = nvk_compile_nir(pdevice, nir, NULL,
-                            &pipeline->base.shaders[MESA_SHADER_COMPUTE]);
+                            &pipeline->base.shaders[MESA_SHADER_COMPUTE], &ctx);
    ralloc_free(nir);
    if (result != VK_SUCCESS)
       goto fail;
diff --git a/src/nouveau/vulkan/nvk_graphics_pipeline.c b/src/nouveau/vulkan/nvk_graphics_pipeline.c
index 219a1bf7a5d..5a5e1fbdf2e 100644
--- a/src/nouveau/vulkan/nvk_graphics_pipeline.c
+++ b/src/nouveau/vulkan/nvk_graphics_pipeline.c
@@ -253,6 +253,10 @@ nvk_graphics_pipeline_create(struct nvk_device *device,
                     state.rp->view_mask != 0, pipeline_layout);
    }
 
+   struct nvk_pipeline_compilation_ctx ctx = {
+      .tesc_domain = MESA_PRIM_POINTS,
+   };
+
    for (gl_shader_stage stage = 0; stage < MESA_SHADER_STAGES; stage++) {
       if (nir[stage] == NULL)
          continue;
@@ -264,7 +268,7 @@ nvk_graphics_pipeline_create(struct nvk_device *device,
       }
 
       result = nvk_compile_nir(pdevice, nir[stage], fs_key,
-                               &pipeline->base.shaders[stage]);
+                               &pipeline->base.shaders[stage], &ctx);
       ralloc_free(nir[stage]);
       if (result != VK_SUCCESS)
          goto fail;
diff --git a/src/nouveau/vulkan/nvk_pipeline.h b/src/nouveau/vulkan/nvk_pipeline.h
index 3313e0a3df0..de1169ec80b 100644
--- a/src/nouveau/vulkan/nvk_pipeline.h
+++ b/src/nouveau/vulkan/nvk_pipeline.h
@@ -65,4 +65,9 @@ nvk_graphics_pipeline_create(struct nvk_device *device,
                              const VkAllocationCallbacks *pAllocator,
                              VkPipeline *pPipeline);
 
+struct nvk_pipeline_compilation_ctx  {
+   uint8_t tesc_domain; // MESA_PRIM_{POINTS, QUADS, TRIANGLES, LINES}
+};
+
+
 #endif
diff --git a/src/nouveau/vulkan/nvk_shader.c b/src/nouveau/vulkan/nvk_shader.c
index dfce17584d3..cb7b77cad34 100644
--- a/src/nouveau/vulkan/nvk_shader.c
+++ b/src/nouveau/vulkan/nvk_shader.c
@@ -1,6 +1,7 @@
 #include "nvk_device.h"
 #include "nvk_shader.h"
 #include "nvk_physical_device.h"
+#include "nvk_pipeline.h"
 
 #include "nouveau_bo.h"
 #include "nouveau_context.h"
@@ -954,7 +955,8 @@ nvk_fill_transform_feedback_state(struct nir_shader *nir,
 VkResult
 nvk_compile_nir(struct nvk_physical_device *device, nir_shader *nir,
                 const struct nvk_fs_key *fs_key,
-                struct nvk_shader *shader)
+                struct nvk_shader *shader,
+                struct nvk_pipeline_compilation_ctx *ctx)
 {
    struct nv50_ir_prog_info *info;
    struct nv50_ir_prog_info_out info_out = {};
@@ -977,6 +979,9 @@ nvk_compile_nir(struct nvk_physical_device *device, nir_shader *nir,
    info->io.auxCBSlot = 1;
    info->io.uboInfoBase = 0;
    info->io.drawInfoBase = 0;
+   if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
+      info->prop.tese.prespecified_domain = ctx->tesc_domain;
+   }
    if (nir->info.stage == MESA_SHADER_COMPUTE) {
       info->prop.cp.gridInfoBase = 0;
    } else {
@@ -1050,6 +1055,10 @@ nvk_compile_nir(struct nvk_physical_device *device, nir_shader *nir,
       }
    }
 
+   if (info->type == PIPE_SHADER_TESS_CTRL) {
+      ctx->tesc_domain = info_out.prop.tp.domain;
+   }
+
    return VK_SUCCESS;
 }
 
diff --git a/src/nouveau/vulkan/nvk_shader.h b/src/nouveau/vulkan/nvk_shader.h
index 8dfde821128..afaf951f506 100644
--- a/src/nouveau/vulkan/nvk_shader.h
+++ b/src/nouveau/vulkan/nvk_shader.h
@@ -11,6 +11,7 @@ struct vk_shader_module;
 struct vk_pipeline_robustness_state;
 struct nvk_device;
 struct nvk_physical_device;
+struct nvk_pipeline_compilation_ctx;
 
 #define GF100_SHADER_HEADER_SIZE (20 * 4)
 #define TU102_SHADER_HEADER_SIZE (32 * 4)
@@ -125,7 +126,8 @@ nvk_lower_nir(struct nvk_device *device, nir_shader *nir,
 VkResult
 nvk_compile_nir(struct nvk_physical_device *device, nir_shader *nir,
                 const struct nvk_fs_key *fs_key,
-                struct nvk_shader *shader);
+                struct nvk_shader *shader,
+                struct nvk_pipeline_compilation_ctx *ctx);
 
 VkResult
 nvk_shader_upload(struct nvk_device *dev, struct nvk_shader *shader);