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brw/nir/rt: ensure we can load 2 RT_DISPATCH_GLOBALS

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Each group of 16 lanes inside a SIMD32 shader will load different globals.

In SIMD8/16 shaders, the divergence analysis will turn this load into
nir_load_global_constant_uniform_block_intel.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
(cherry picked from commit 527ae448e5)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39462>
This commit is contained in:
Lionel Landwerlin 2025-07-16 23:29:18 +03:00 • committed by Dylan Baker
parent b9797ce180
commit 92544a389b
2 changed files with 2 additions and 2 deletions
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2
.pick_status.json
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@ -1364,7 +1364,7 @@
"description": "brw/nir/rt: ensure we can load 2 RT_DISPATCH_GLOBALS",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": null,
"notes": null

2
src/intel/compiler/brw/brw_nir_rt_builder.h
View file

@ -62,7 +62,7 @@ brw_nir_rt_store(nir_builder *b, nir_def *addr, unsigned align,
static inline nir_def *
brw_nir_rt_load_const(nir_builder *b, unsigned components, nir_def *addr)
{
return nir_load_global_constant_uniform_block_intel(
return nir_build_load_global_constant(
b, components, 32, addr,
.access = ACCESS_CAN_REORDER | ACCESS_NON_WRITEABLE,
.align_mul = 64);