From 92544a389bba31e78244c38f69cb1d344c20a857 Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Wed, 16 Jul 2025 23:29:18 +0300 Subject: [PATCH] brw/nir/rt: ensure we can load 2 RT_DISPATCH_GLOBALS Each group of 16 lanes inside a SIMD32 shader will load different globals. In SIMD8/16 shaders, the divergence analysis will turn this load into nir_load_global_constant_uniform_block_intel. Signed-off-by: Lionel Landwerlin Cc: mesa-stable Reviewed-by: Sagar Ghuge (cherry picked from commit 527ae448e5fa67dc32926161bf6db6f14124feac) Part-of: --- .pick_status.json | 2 +- src/intel/compiler/brw/brw_nir_rt_builder.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.pick_status.json b/.pick_status.json index 3c6f78e1eca..e4f1c419f90 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -1364,7 +1364,7 @@ "description": "brw/nir/rt: ensure we can load 2 RT_DISPATCH_GLOBALS", "nominated": true, "nomination_type": 1, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": null, "notes": null diff --git a/src/intel/compiler/brw/brw_nir_rt_builder.h b/src/intel/compiler/brw/brw_nir_rt_builder.h index 1ff103ec757..c3c8bfb804b 100644 --- a/src/intel/compiler/brw/brw_nir_rt_builder.h +++ b/src/intel/compiler/brw/brw_nir_rt_builder.h @@ -62,7 +62,7 @@ brw_nir_rt_store(nir_builder *b, nir_def *addr, unsigned align, static inline nir_def * brw_nir_rt_load_const(nir_builder *b, unsigned components, nir_def *addr) { - return nir_load_global_constant_uniform_block_intel( + return nir_build_load_global_constant( b, components, 32, addr, .access = ACCESS_CAN_REORDER | ACCESS_NON_WRITEABLE, .align_mul = 64);