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iris: Specify Untyped L1 cache policy for stateless accesses

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Set write back L1 cache policy in STATE_BASE_ADDRESS instruction for A64
messages.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16905>
This commit is contained in:
Sagar Ghuge 2021-08-16 12:29:37 -07:00 • committed by Lionel Landwerlin
parent 79cd2c2759
commit 8aead60434
1 changed files with 6 additions and 0 deletions
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6
src/gallium/drivers/iris/iris_state.c
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@ -739,6 +739,9 @@ init_state_base_address(struct iris_batch *batch)
sba.IndirectObjectBufferSize = 0xfffff;
sba.InstructionBufferSize = 0xfffff;
sba.DynamicStateBufferSize = 0xfffff;
#if GFX_VERx10 >= 125
sba.L1CacheControl = L1CC_WB;
#endif
}
flush_after_state_base_change(batch);
@ -5500,6 +5503,9 @@ iris_update_binder_address(struct iris_batch *batch,
sba.SurfaceStateMOCS = mocs;
#if GFX_VER >= 9
sba.BindlessSurfaceStateMOCS = mocs;
#endif
#if GFX_VERx10 >= 125
sba.L1CacheControl = L1CC_WB;
#endif
}
#endif