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anv: Specify Untyped L1 cache policy for stateless accesses

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Set write back L1 cache policy in STATE_BASE_ADDRESS instruction for A64
messages.

v2: Also set the value in genX_state.c (Lionel)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16905>
This commit is contained in:
Sagar Ghuge 2021-08-16 12:16:49 -07:00 • committed by Lionel Landwerlin
parent d4b2b769d1
commit 79cd2c2759
2 changed files with 5 additions and 0 deletions
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3
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -224,6 +224,9 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
sba.BindlessSamplerStateBaseAddressModifyEnable = true;
sba.BindlessSamplerStateBufferSize = 0;
# endif
#if GFX_VERx10 >= 125
sba.L1CacheControl = L1CC_WB;
#endif
}
#if GFX_VERx10 == 120

2
src/intel/vulkan/genX_state.c
View file

@ -224,6 +224,8 @@ init_common_queue_state(struct anv_queue *queue, struct anv_batch *batch)
sba.BindlessSamplerStateMOCS = mocs;
sba.BindlessSamplerStateBaseAddressModifyEnable = true;
sba.BindlessSamplerStateBufferSize = 0;
sba.L1CacheControl = L1CC_WB;
}
#endif
}