From 8aead60434aa0babf656738a577298ca09805fd2 Mon Sep 17 00:00:00 2001
From: Sagar Ghuge <sagar.ghuge@intel.com>
Date: Mon, 16 Aug 2021 12:29:37 -0700
Subject: [PATCH] iris: Specify Untyped L1 cache policy for stateless accesses

Set write back L1 cache policy in STATE_BASE_ADDRESS instruction for A64
messages.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16905>
---
 src/gallium/drivers/iris/iris_state.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index 88b07415dbc..1cf2ddec702 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -739,6 +739,9 @@ init_state_base_address(struct iris_batch *batch)
       sba.IndirectObjectBufferSize = 0xfffff;
       sba.InstructionBufferSize    = 0xfffff;
       sba.DynamicStateBufferSize   = 0xfffff;
+#if GFX_VERx10 >= 125
+      sba.L1CacheControl = L1CC_WB;
+#endif
    }
 
    flush_after_state_base_change(batch);
@@ -5500,6 +5503,9 @@ iris_update_binder_address(struct iris_batch *batch,
       sba.SurfaceStateMOCS            = mocs;
 #if GFX_VER >= 9
       sba.BindlessSurfaceStateMOCS    = mocs;
+#endif
+#if GFX_VERx10 >= 125
+      sba.L1CacheControl = L1CC_WB;
 #endif
    }
 #endif