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brw: Add missed access to store_urb_lsc_intel intrinsics

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I forgot to copy this over in the LSC case.  This meant we were missing
reorderability which meant that we were missing out on CSE.

fossil-db results on Battlemage:

   Instrs: 231471427 -> 231363032 (-0.05%)
   Send messages: 12077759 -> 12019628 (-0.48%)
   Cycle count: 34058451430.0 -> 34057005552.0 (-0.00%); split: -0.01%, +0.00%
   Spill count: 520387 -> 520135 (-0.05%)
   Fill count: 470812 -> 470722 (-0.02%)
   Max live registers: 72111834 -> 71873886 (-0.33%)

   Totals from 2898 (0.37% of 788851) affected shaders:
   Instrs: 1223836 -> 1115441 (-8.86%)
   Send messages: 148633 -> 90502 (-39.11%)
   Cycle count: 17732554.0 -> 16286676.0 (-8.15%); split: -10.65%, +2.49%
   Spill count: 252 -> 0 (-inf%)
   Fill count: 90 -> 0 (-inf%)
   Max live registers: 491684 -> 253736 (-48.39%)
   Non SSA regs after NIR: 255397 -> 255402 (+0.00%)

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38918>
This commit is contained in:
Kenneth Graunke 2025-12-11 01:49:13 -08:00 • committed by Marge Bot
parent 87c63b4725
commit 8177695403
1 changed files with 2 additions and 1 deletions
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3
src/intel/compiler/brw/brw_nir.c
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@ -158,7 +158,8 @@ load_urb(nir_builder *b,
if (devinfo->ver >= 20) {
nir_def *addr = nir_iadd(b, handle, nir_ishl_imm(b, offset, 4));
return nir_load_urb_lsc_intel(b, intrin->def.num_components, bits, addr,
16 * base + 4 * io_component(intrin));
16 * base + 4 * io_component(intrin),
.access = access);
}
/* Load a whole vec4 and return the desired portion */