From 817769540329a1cd2250db3fb6c3810a8b4ad3b7 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Thu, 11 Dec 2025 01:49:13 -0800 Subject: [PATCH] brw: Add missed access to store_urb_lsc_intel intrinsics I forgot to copy this over in the LSC case. This meant we were missing reorderability which meant that we were missing out on CSE. fossil-db results on Battlemage: Instrs: 231471427 -> 231363032 (-0.05%) Send messages: 12077759 -> 12019628 (-0.48%) Cycle count: 34058451430.0 -> 34057005552.0 (-0.00%); split: -0.01%, +0.00% Spill count: 520387 -> 520135 (-0.05%) Fill count: 470812 -> 470722 (-0.02%) Max live registers: 72111834 -> 71873886 (-0.33%) Totals from 2898 (0.37% of 788851) affected shaders: Instrs: 1223836 -> 1115441 (-8.86%) Send messages: 148633 -> 90502 (-39.11%) Cycle count: 17732554.0 -> 16286676.0 (-8.15%); split: -10.65%, +2.49% Spill count: 252 -> 0 (-inf%) Fill count: 90 -> 0 (-inf%) Max live registers: 491684 -> 253736 (-48.39%) Non SSA regs after NIR: 255397 -> 255402 (+0.00%) Reviewed-by: Alyssa Rosenzweig Part-of: --- src/intel/compiler/brw/brw_nir.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw/brw_nir.c b/src/intel/compiler/brw/brw_nir.c index 33d7e0c9ff8..f5fc109d7cd 100644 --- a/src/intel/compiler/brw/brw_nir.c +++ b/src/intel/compiler/brw/brw_nir.c @@ -158,7 +158,8 @@ load_urb(nir_builder *b, if (devinfo->ver >= 20) { nir_def *addr = nir_iadd(b, handle, nir_ishl_imm(b, offset, 4)); return nir_load_urb_lsc_intel(b, intrin->def.num_components, bits, addr, - 16 * base + 4 * io_component(intrin)); + 16 * base + 4 * io_component(intrin), + .access = access); } /* Load a whole vec4 and return the desired portion */