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i965/skl: Use 1 register for uniform pull constant payload

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When under dispatch_width=16 the previous code would allocate 2 registers for
the payload when only one is needed. This manifested itself through bugs on SKL
which needs to mess with this instruction.

Ken thought this might impact shader-db, but apparently it doesn't

Backported to 10.5.8 from (upstream uses alloc.allocate()):
commit 6e62a52865
Author: Ben Widawsky <benjamin.widawsky@intel.com>
Date:   Thu Feb 19 15:49:34 2015 -0800

    i965/skl: Use 1 register for uniform pull constant payload

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89118
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88999
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Timo Aaltonen <timo.aaltonen@canonical.com>
Cc: "10.5" <mesa-stable@lists.freedesktop.org>
This commit is contained in:
Ben Widawsky 2015-06-22 17:18:02 -07:00 • committed by Emil Velikov
parent 999b2b2716
commit 80e283b053
1 changed files with 1 additions and 1 deletions
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2
src/mesa/drivers/dri/i965/brw_fs.cpp
View file

@ -3039,7 +3039,7 @@ fs_visitor::lower_uniform_pull_constant_loads()
assert(const_offset_reg.file == IMM &&
const_offset_reg.type == BRW_REGISTER_TYPE_UD);
const_offset_reg.fixed_hw_reg.dw1.ud /= 4;
fs_reg payload = vgrf(glsl_type::uint_type);
fs_reg payload = fs_reg(GRF, virtual_grf_alloc(1));
/* We have to use a message header on Skylake to get SIMD4x2 mode.
* Reserve space for the register.