diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index f72d13d6ce3..b54e4d73e82 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -3039,7 +3039,7 @@ fs_visitor::lower_uniform_pull_constant_loads()
          assert(const_offset_reg.file == IMM &&
                 const_offset_reg.type == BRW_REGISTER_TYPE_UD);
          const_offset_reg.fixed_hw_reg.dw1.ud /= 4;
-         fs_reg payload = vgrf(glsl_type::uint_type);
+         fs_reg payload = fs_reg(GRF, virtual_grf_alloc(1));
 
          /* We have to use a message header on Skylake to get SIMD4x2 mode.
           * Reserve space for the register.