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i965/skl: Use 1 register for uniform pull constant payload

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When under dispatch_width=16 the previous code would allocate 2 registers for
the payload when only one is needed. This manifested itself through bugs on SKL
which needs to mess with this instruction.

Ken though this might impact shader-db, but apparently it doesn't

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89118
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88999
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Timo Aaltonen <timo.aaltonen@canonical.com>
This commit is contained in:
Ben Widawsky 2015-02-19 15:49:34 -08:00
parent 4359954d84
commit 6e62a52865
1 changed files with 1 additions and 1 deletions
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2
src/mesa/drivers/dri/i965/brw_fs.cpp
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@ -3063,7 +3063,7 @@ fs_visitor::lower_uniform_pull_constant_loads()
assert(const_offset_reg.file == IMM &&
const_offset_reg.type == BRW_REGISTER_TYPE_UD);
const_offset_reg.fixed_hw_reg.dw1.ud /= 4;
fs_reg payload = vgrf(glsl_type::uint_type);
fs_reg payload = fs_reg(GRF, alloc.allocate(1));
/* We have to use a message header on Skylake to get SIMD4x2 mode.
* Reserve space for the register.