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anv: set DisableAnyMCTRresponsefix to zero on init

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This is to make sure early culling related Wa_16020518922 is enabled
properly.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14204
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
(cherry picked from commit 9aaed82543)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39969>
This commit is contained in:
Tapani Pälli 2026-02-05 10:10:18 +02:00 • committed by Dylan Baker
parent 971709661d
commit 79796e0db4
2 changed files with 12 additions and 1 deletions
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2
.pick_status.json
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@ -1114,7 +1114,7 @@
"description": "anv: set DisableAnyMCTRresponsefix to zero on init",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": null,
"notes": null

11
src/intel/vulkan/genX_init_state.c
View file

@ -625,6 +625,17 @@ init_render_queue_state(struct anv_queue *queue, bool is_companion_rcs_batch)
}
#endif
#if GFX_VERx10 >= 300
/* Set value explicitly on init to override possible wrong setting. This bit
* default changed from Xe2 to Xe3 and is required to be zero for
* Wa_16020518922 as mentioned in bspec 55893.
*/
anv_batch_write_reg(batch, GENX(CHICKEN_RASTER_2), reg) {
reg.DisableAnyMCTRresponsefix = false;
reg.DisableAnyMCTRresponsefixMask = true;
}
#endif
/* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so
* 3DSTATE_CONSTANT_XS buffer 0 is an absolute address.
*