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intel/genxml: add CHICKEN_RASTER_2 with required bit for Xe3

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Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
(cherry picked from commit 61b5e91bba)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39969>
This commit is contained in:
Tapani Pälli 2026-02-05 10:09:34 +02:00 • committed by Dylan Baker
parent daf7817e5c
commit 971709661d
2 changed files with 5 additions and 1 deletions
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2
.pick_status.json
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@ -1124,7 +1124,7 @@
"description": "intel/genxml: add CHICKEN_RASTER_2 with required bit for Xe3",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": null,
"notes": null

4
src/intel/genxml/gen300.xml
View file

@ -809,4 +809,8 @@
<field name="UAV Coherency Mode Mask" dword="2" bits="22:22" type="uint" />
<field name="Memory allocation for Scratch and Midthread Preemption buffers Mask" dword="2" bits="27:27" type="uint" />
</instruction>
<register name="CHICKEN_RASTER_2" length="1" num="0x6208">
<field name="Disable Any MCTR response fix" dword="0" bits="5:5" type="bool" />
<field name="Disable Any MCTR response fix Mask" dword="0" bits="21:21" type="bool" />
</register>
</genxml>