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ir3/legalize: handle scalar ALU WAR hazards for a0.x

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It turns out that mova executes on the normal pipeline, which means that
users of a0.x on the scalar pipeline might cause a WAR hazard with mova.

Fixes: 876c5396a7 ("ir3: Add support for "scalar ALU"")
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28341>
This commit is contained in:
Job Noorman 2024-08-15 08:46:36 +02:00 • committed by Marge Bot
parent dead168200
commit 72bb4d79dc
2 changed files with 7 additions and 1 deletions
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6
src/freedreno/ir3/ir3.h
View file

@ -1416,6 +1416,12 @@ is_reg_gpr(const struct ir3_register *reg)
return true; return true;
} }
static inline bool
is_reg_a0(const struct ir3_register *reg)
{
return reg->num == regid(REG_A0, 0);
}
/* is dst a normal temp register: */ /* is dst a normal temp register: */
static inline bool static inline bool
is_dest_gpr(const struct ir3_register *dst) is_dest_gpr(const struct ir3_register *dst)

2
src/freedreno/ir3/ir3_legalize.c
View file

@ -647,7 +647,7 @@ legalize_block(struct ir3_legalize_ctx *ctx, struct ir3_block *block)
* need to wait for previous ones. * need to wait for previous ones.
*/ */
foreach_src (reg, n) { foreach_src (reg, n) {
if (reg->flags & IR3_REG_SHARED) { if ((reg->flags & IR3_REG_SHARED) || is_reg_a0(reg)) {
regmask_set(&state->needs_ss_scalar_war, reg); regmask_set(&state->needs_ss_scalar_war, reg);
} }
} }